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In this abstract we present a highly manufacturable, high performance 90nm technology with best in class ,performance for 35nm gate-length N and P transistors. Unique, but simple and low cost, process changes have been utilized to modulate channel stress and implant profile to generate enhanced performance with no additional masks. High drive currents of 1193uAium and 587uAium are obtained for nMOS and PMOS transistors respectively at I .2V Vdd and an Ioff of 60nMpm. An industry leading 90nm technology CVil of 0 . 6 1~s and 1 .

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We report the integration of six levels of Cu interconnects using dual inlaid patterning in a 0.2 μm logic technology. A review of process technology as well as device performance shortcomings using conventional aluminum metallization has been presented. Two tantalum based barriers, TaNx and Ta-Si-N as well as a titanium based barrier, CVD TiN, have been evaluated for their applicability. The use of embedded barriers wherein the barrier is formed below the surface of the dielectric has also been discussed as a potential option. No degradation to the device front-end parametrics were found with the choice of an appropriate barrier. Planarization by Cu CMP introduces surface topography that needs to be minimized in order to process multiple levels of interconnects within specified sheet resistance distributions for a range of line widths. Excellent results with highly planarized levels of metallization have consistently been achieved through an optimization of the unit processes and device integration.