Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs

Song, Taigon; Liu, Chang; Kim, Dae Hyun; Lim, Sung Kyu; Cho, Jonghyun; Kim, Joohee; Pak, Jun So; Ahn, Seungyoung; Kim, Joungho; Yoon, Kwan Han

doi:10.1109/isqed.2011.5770714

Cited by 29 publications

(8 citation statements)

References 6 publications

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“…In this paper, on the basis of a result of the paper [2] and [3] for the purpose of applying the full-chip 3D IC design, we analyzed the impedance effect among the TSVs according to input frequency and analyzed impedance of the TSV-to-TSV in a multiple TSVto-TSVs in order to use as parameter of 3D IC design.…”

Section:   mentioning

confidence: 99%

The Impedance Analysis of Multiple TSV-to-TSV

Lee¹

2016

Journal of the Institute of Electronics and Information Enginee

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In this paper, we analyze the impedance analysis of vertical interconnection through-silicon vias (TSV) that is being studied for the purpose of improving the degree of integration and an electric feature in 3D IC. Also, it is to improve the performance and the degree of integration of the three-dimensional integrated circuit system which can exceed the limits of conventional two-dimensional a IC. In the future, TSV technology in full-chip 3-dimensional integrated circuit system design is very important, and a study on the electrical characteristics of the TSV for high-density and high-bandwidth system design is very important. Therefore, we study analyze the impedance influence of the TSV in accordance with the distance and frequency in a multiple TSV-to-TSV for the purpose of designing a full-chip three-dimensional IC. The results of this study also are applicable to semiconductor process tools and designed for the manufacture of a full-chip 3D IC.

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Section:   mentioning

confidence: 99%

The Impedance Analysis of Multiple TSV-to-TSV

Lee¹

2016

Journal of the Institute of Electronics and Information Enginee

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“…The resistance R and inductance L of TSVs are calculated from existing formulas [1]- [5], while the C g , R g , C Si , and R Si shown in Fig. 3 are obtained with a 3D field solver (Synopsys Raphael).…”

Section: A Physical and Electrical Parametersmentioning

confidence: 99%

“…Lumped RLGC element models for TSVs and the areas surrounding TSVs have been proposed [1]- [5]. These models can easily calculate the resistance, inductance, and capacitance of TSVs, but, they do not include the effect grounded by substrate contacts.…”

Section: Introductionmentioning

confidence: 99%

Effect of substrate contacts on reducing crosstalk noise between TSVs

Watanabe

Karel

Niioka

et al. 2014

2014 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)

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We propose a model for coupling that considers substrate contacts between through silicon vias (TSVs) in bulk-CMOS technologies. The proposed model is compact but has reasonable accuracy for the dense substrate contacts in largescale three dimensional integrated circuits (3D ICs). We describe the modeling for substrate contacts with the equivalent electrical circuit, discuss the impact of substrate contacts on the electrical parasitic parameters, and clarify the effect of substrate contacts on reducing crosstalk noise and increasing delay. Results of analysis show that if substrate contacts are not considered, crosstalk noise becomes the overestimate of 5 to 700 times and delay becomes the underestimate of 1.4 to 2.4 times.

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“…3D Interconnect is the promising technology [1]- [4], which includes Through-Silicon-Vias (TSVs) to connect vertically stacked semiconductor chips with shortest paths, which means lowest inductance and conduction loss, to both signals and power supplies. In spite of these benefits, the signal integrity issues in TSVs become the major challenges in 3D designs [5][6]. The goal of TSVs or 3D Vias development is to acquire high chip density.…”

Section: Introductionmentioning

confidence: 99%

Impact of Crosstalk on Signal Integrity of TSVs in 3D Integrated Circuits

Harb¹,

Eisenstadt²

2018

Adv. sci. technol. eng. syst. j.

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Through-Silicon-Vias (TSVs) are utilized for high density 3D integration, which induce crosstalk problems and impact signal integrity. This paper focuses on TSV crosstalk characterization in 3D integrated circuits, where several TSV physical and environmental configurations are investigated. In particular, this work shows a detailed study on the influence of signal-ground TSV locations, distances and their structural configurations on crosstalk. Embedded 3D testing circuits are also presented to evaluate the coupling effects between adjacent TSVs such as crosstalk induced delay and glitches for different crosstalk modes. Additionally, A 3D parallel Ring Oscillators testing structure is proposed to provide crosstalk strength coupling indicator between adjacent TSVs. Simulation results are conducted using a 3D electromagnetic field solver (HFSS) from Ansoft Corporation and a Spice-like simulator (ADS) from Keysight Technologies Corporation based on MIT 0.15µm 3DFDSOI process technology.

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Analysis of TSV-to-TSV coupling with high-impedance termination in 3D ICs

Cited by 29 publications

References 6 publications

The Impedance Analysis of Multiple TSV-to-TSV

The Impedance Analysis of Multiple TSV-to-TSV

Effect of substrate contacts on reducing crosstalk noise between TSVs

Impact of Crosstalk on Signal Integrity of TSVs in 3D Integrated Circuits

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