Analysis of Within-Die Complementary Metal–Oxide–Semiconductor Process Variation with Reconfigurable Ring Oscillator Arrays Using HiSIM

Abstract

A pulsed glow discharge is used for sputtering in the presence of a gas flow to form a metal vapour jet suitable for use in a room-temperature metal vapour laser. It is found that the sputtering process is most efficient during the first 50 ps of the discharge pulse. Switching the discharge in the burst mode with a pulse duration of about 15 ps and an interpulse delay of about 18 ps achieves similar metal vapour concentrations in the jet to that attained by steady-pulse sputtering, but requires only half the total discharge energy.

Experimental Analysis of Within-Die Process Variation in 65 and 180 nm Complementary Metal–Oxide–Semiconductor Technology Including Its Distance Dependences

“…The data for horizontal variation in the rows verifies that the 3= (%) values are about 3-7 times larger for the case of the 65 nm technology, although the size of the ring-oscillator-array in the 180 nm technology design is almost 1.62 times larger than in the 65 nm technology design. 7) Similarly, for a fixed m-th stage with activated path2 for all P rows, we get Hmj ¼ HPmj À HTj . And hence, with these measurement data, we found that in the vertical direction, the 3= (%) values for the 65 nm technology are quite consistent with those in horizontal direction, as summarized in Table III.…”

“…On the other hand, the vertical variation in 180 nm technology analysis is substantially larger than in horizontal direction, which we attribute to a systematic variation effect along the vertical direction during the respective wafer fabrication. 7) We have also studied the voltage dependence of the variation magnitude and of the position dependence in 65 nm technology. Table IV presents the trend of variation along horizontal direction for different row locations in die 1 at nominal core voltage (1.2 V) and at a reduced core-voltage level of (0.7 V).…”

“…Since the sources of global and local process variation are different, 5,6) variation is categorized into within wafer, die-to-die and within-die variation. 7,8,17) Within wafer and die-to-die fluctuations affect every element in an IC in the same way. On the other side, within-die variations cause a random nonuniformity of physical characteristics among the devices in an IC.…”

“…11) Studies of the variation at the circuit level have typically focused on small ring oscillators where frequency or delay of the ring oscillator is used to characterize variation at both within-die and die to die levels. 7,[12][13][14][15][16][17] Here, we report an analysis of the two-dimensional variation in a 1:3 Â 1:28 mm 2 test chip, fabricated with 65 nm complementary metal-oxide-semiconductor (CMOS) technology, at nominal and reduced supply voltage levels using the delay of a ring oscillator with adjustable delay stages. It was found that the random delay variation within the die at reduced voltage of 0.7 V has a 3= value (: standard deviation, : mean value of the delay) of 16-28% whereas the 3= value at nominal voltage of 1.2 V is reduced to only 5-7%, i.e., is a factor 3 smaller.…”