2020 International Conference on Emerging Trends in Communication, Control and Computing (ICONC3) 2020
DOI: 10.1109/iconc345789.2020.9117425
|View full text |Cite
|
Sign up to set email alerts
|

Analysis on Variations of Metal Gate Work Function on Junctionless Double Gate MOSFET with High-k Spacers

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...
1
1

Citation Types

1
3
0

Year Published

2021
2021
2023
2023

Publication Types

Select...
3
1

Relationship

0
4

Authors

Journals

citations
Cited by 4 publications
(4 citation statements)
references
References 14 publications
1
3
0
Order By: Relevance
“…As for n-JLSDGM device, decreasing the WF would contribute to lower V th , thus increasing the I ON . This is in agreement with the results reported by [21], [29], [35]. Based on the results, the highest recorded I ON is demonstrated by the n-JLSDGM device with WF=4.6 which is measured at approximately 1951 µA/µm.…”
Section: Electrostatic Performancessupporting
confidence: 92%
See 1 more Smart Citation
“…As for n-JLSDGM device, decreasing the WF would contribute to lower V th , thus increasing the I ON . This is in agreement with the results reported by [21], [29], [35]. Based on the results, the highest recorded I ON is demonstrated by the n-JLSDGM device with WF=4.6 which is measured at approximately 1951 µA/µm.…”
Section: Electrostatic Performancessupporting
confidence: 92%
“…High-k/metal-gate (HKMG) stack technology is one the common approach to control the gate leakage current [18]- [20]. The HKMG integration offers an alternative option in minimizing the gate leakage without having to reduce the thickness of the insulator for same intrinsic capacitances [21]. Rezeli et al have stated that parameter dependencies should be carefully considered in HKMG based transistor due to inconsistent atom configuration at the surface material [15].…”
Section: Introductionmentioning
confidence: 99%
“…22 Junctionless Gate all around FET are the most promising contender because of their resistance to short-channel effects (SCEs) and the random dopant profile effect. 23,24 The Junctionless FET device architecture eliminates the need for metallurgical junctions, thereby eliminating the ultra-steep doping profile required between the source/drain and channel regions, along with the complex thermal budget requirements associated with it. 25 But, Junctionless FETs face challenges including high source-drain resistance, lower mobility, and band-to-band tunnelling 26 in the OFF state.…”
mentioning
confidence: 99%
“…34,35 When making small-scale devices, the silicon dioxide (SiO 2 ) gate insulator should be replaced with a high-k dielectric gate oxide material, such as hafnium oxide, while maintaining appropriate z E-mail: shivaniyadav.ece@gmail.com; rewarisonam@gmail.com ECS Journal of Solid State Science and Technology, 2023 12 127008 oxide thickness (EOT) as a constant. 23 Hetero Dielectric structure in which combinations of low dielectric material together with high dielectric materials are utilised for FETs have been reported in literature to boost ON current 36 and reduce the OFF state leakages. 37,38 Nanometer sized biomolecules are detectable using Gate All Around Field Effect Transistor (GAAFET) based sensors.…”
mentioning
confidence: 99%