Analytical model for random dopant fluctuation in double-gate MOSFET in the subthreshold region using macroscopic modeling method

Shin, Young-Han; Yun, Ilgu

doi:10.1016/j.sse.2016.08.006

Cited by 8 publications

(4 citation statements)

References 22 publications

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“…The old MOSFET transistors used in the past were made of two p-n junctions with an effective channel length designed between them. MOSFET technology has reached its limits from the point of view of miniaturization, imposed by the gate tunneling current and the adverse short channel effects (SCEs) [1,2]. This is why many new multiple gate structures such as double-gate (DG) [3], triple-gate (TG) [4], -gate [5], -gate [6], quadruple-gate (QG) and surrounding gate MOSFETs [7,8] have become coveted research topics because of their high gate control ability and their high scaling [6].…”

Section: Introductionmentioning

confidence: 99%

Channel Length Effect on Subthreshold Characteristics of Junctionless Trial Material Cylindrical Surrounding-Gate MOSFETs with High-k Gate Dielectrics

Lagraf¹,

Djamil²,

Guergouri³

et al. 2019

J. Nano- Electron. Phys.

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The intensive decrease of channel length for a MOS transistor imposes extensive constraints notably for controlling the short channel effects (SCEs) in nanoscale MOSFET. These constraints can degrade the device performance, hence determining the limits of miniaturization of MOSFET in nanoelectronics applications. In order to reduce the degree of SCEs, a number of new architectures have been reported. Due to their higher scaling capabilities, the double-gate (DG) MOSFETs are expected to be maintained in future nanoelectronics applications. However, with the continuous miniaturization other serious challenges related to the maximum power dissipation and the fabrication cost still persist owing to the high cost techniques used for the elaboration of the p-n junctions. Recently, a new design called junctionless MOSFET without source/drain junctions has been proposed to be an excellent alternative to the conventional MOSFET. The major advantage of this structure resides on the enhanced fabrication procedure through the elimination of the p-n junctions. In this work, the impact of channel length and high-k gate dielectrics materials on the subthreshold characteristics of junctionless trial material cylindrical surrounding-gate MOSFETs (JLTMCSG-MOSFETs) with high-k gate dielectrics and trial material (TM) structure has been studied using two-dimensional analytical model. This model is based on the solution of Poisson's equation in continuous cylindrical regions using superposition method, where the Fourier-Bessel series and separation method have been used to obtain the accurate solution. The performance of low power JLTMCSG-MOSFETs is investigated in terms of surface potential distribution, electrical field, subthreshold current, drain induced barrier lowering (DIBL), subthreshold slope (SS) and threshold voltage (Vth). This study is carried out over a wide range of channel lengths and using high-k gate dielectrics. This study confirms that the analytical model used is useful not only for circuit simulations, but also for device design and optimization for both logic and analog RF circuits applications.

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Section: Introductionmentioning

confidence: 99%

Channel Length Effect on Subthreshold Characteristics of Junctionless Trial Material Cylindrical Surrounding-Gate MOSFETs with High-k Gate Dielectrics

Lagraf¹,

Djamil²,

Guergouri³

et al. 2019

J. Nano- Electron. Phys.

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“…14) An analytical model in double-gate MOSFETs in the subthreshold region using the macroscopic modeling method has been proposed to predict the variations in electrical characteristics caused by RDF. 15) Andrei and Oniciuc 16) developed a method of suppressing the effect of random doping on the device V th .…”

Section: Introductionmentioning

confidence: 99%

Modeling the threshold voltage variation induced by channel random dopant fluctuation in fully depleted silicon-on-insulator MOSFETs

Zhang

Yang

Jiang

et al. 2018

Jpn. J. Appl. Phys.

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In nanoscale fully depleted silicon-on-insulator (FD-SOI) MOSFETs, the standard deviation of threshold voltage (σVth) caused by random dopant fluctuation (RDF) is an important parameter to predict the performance of transistors and circuits. In this paper, an analytic model of σVth considering both the dopant “number” and dopant “position” fluctuation in channels is proposed. A new model of σVth,num caused by “number” is given and the method of obtaining the “position” influence ratio Rp is discussed in this paper. Moreover, the simulation methods are analyzed in detail. The calculated σVth values in FD-SOI MOSFETs are compared with the Sentaurus TCAD simulation results at different channel lengths, channel doping concentrations, SOI film thicknesses, front gate oxide thicknesses, and buried-oxide thicknesses. The comparison shows that the proposed model matches well with the obtained numerical simulation results.

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“…As the transistor channel length shrinks, and approaches a few nanometers, the distribution of impurity atoms becomes discrete, due to the low number of dopant atoms in the channel region. For example, in a JNT gate-all-around (GAA) rectangular FET with 5 nm channel length and cross-sectional area of 5×5 nm 2 , and with body doping density of 1×10 20 cm −3 , there will be approximately 12 dopant atoms in the channel region. The discrete and random nature of the impurity atom distribution, and their specific stochastic position in the device structure, is expected to greatly affect the performance of such devices [15,16].…”

Section: Introductionmentioning

confidence: 99%

“…It will be shown that, by optimizing doping density in a JNT device geometry, the variability in device characteristics can be significantly minimized. In addition, it is theoretically demonstrated that a 5 nm gate length JNT can be realized with relatively low stochastic RDF variability; thus, in principle, JNTs can be employed to further advance scaling in silicon-based CMOS technology [7][8][9][19][20][21][22].…”

Section: Introductionmentioning

confidence: 99%

Random dopant fluctuations and statistical variability in n-channel junctionless FETs

Akhavan

Umana‐Membreno²,

Gu³

et al. 2017

Nanotechnology

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The influence of random dopant fluctuations on the statistical variability of the electrical characteristics of n-channel silicon junctionless nanowire transistor (JNT) has been studied using three dimensional quantum simulations based on the non-equilibrium Green's function (NEGF) formalism. Average randomly distributed body doping densities of 2 × 10, 6 × 10 and 1 × 10 cm have been considered employing an atomistic model for JNTs with gate lengths of 5, 10 and 15 nm. We demonstrate that by properly adjusting the doping density in the JNT, a near ideal statistical variability and electrical performance can be achieved, which can pave the way for the continuation of scaling in silicon CMOS technology.

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Analytical model for random dopant fluctuation in double-gate MOSFET in the subthreshold region using macroscopic modeling method

Cited by 8 publications

References 22 publications

Channel Length Effect on Subthreshold Characteristics of Junctionless Trial Material Cylindrical Surrounding-Gate MOSFETs with High-k Gate Dielectrics

Channel Length Effect on Subthreshold Characteristics of Junctionless Trial Material Cylindrical Surrounding-Gate MOSFETs with High-k Gate Dielectrics

Modeling the threshold voltage variation induced by channel random dopant fluctuation in fully depleted silicon-on-insulator MOSFETs

Random dopant fluctuations and statistical variability in n-channel junctionless FETs

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