Random dopant fluctuations and statistical variability in n-channel junctionless FETs

Akhavan, Nima Dehdashti; Umana‐Membreno, Gilberto A.; Gu, Runxia; Antoszewski, J.; Faraone, Lorenzo

doi:10.1088/1361-6528/aa9d45

Cited by 12 publications

(4 citation statements)

References 32 publications

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“…The doping concentration of Ge nanowire is set within 1 × 10 19 cm −3 to 3 × 10 19 cm −3 to observe the change of RDF process variation by different doping concentrations. Note that Ge doping concentrations below 3 × 10 19 cm −3 are required to meet the ITRS subthreshold swing target based on our previous work [6]. In case of the metal gate work function, it is calibrated to make the devices obtain off-state current of 1 nA/um; for this reason, 4.83, 4.93, and 5.03 eV are applied for each Ge doping concentration.…”

Section: Device Design and Simulation Methodsmentioning

confidence: 99%

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Impact of Random Dopant Fluctuation on n-Type Ge Junctionless FinFETs With Metal–Interlayer–Semiconductor Source/Drain Contact Structure

Jung

2019

IEEE J. Electron Devices Soc.

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The impact of random dopant fluctuation (RDF) on n-type Ge junctionless FinFETs (JLFETs) with metal-interlayer-semiconductor (MIS) source/drain (S/D) contact structure is firstly investigated via 3-D technology computer aided design (TCAD) simulations. The estimation and evaluation of standard deviations in threshold voltage (V th ), on-state current (I on ), off-state current (I off ), subthreshold swing (SS), and drain induced barrier lowering (DIBL) by different Ge nanowire doping concentrations and different heights for RDF effects are performed. The results show a decreasing trend of RDF with lower doping concentration of the device. Furthermore, the influence of MIS S/D on RDF of n-type Ge JLFET is assessed through a comparative analysis between an n-type Ge JLFETs with and without MIS S/D structure. The analysis results estimate that MIS S/D can reduce performance variation to approximately 0.0237 V for σ V th , 5.75 × 10 −5 A/um for σ I on , 4.30 × 10 −10 A/um for σ I off , 0.548 mV/dec for σ SS, and 12.3 mV/V for DIBL, without severe performance degradation of the current nominal values. This estimation gives a significant insight on variability prediction of the 7 nm n-type Ge JLFET device with MIS S/D structure.

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Section: Device Design and Simulation Methodsmentioning

confidence: 99%

“…The electrical characteristics of JLFETs strongly depend on doping concentration and the dimension of semiconductor nanowires, so the sensitivity of their performance variation by random dopant fluctuation (RDF) is at a highly vulnerable position [6]- [9]. This calls as well for an imperative evaluation of this performance variability.…”

Section: Introductionmentioning

confidence: 99%

Impact of Random Dopant Fluctuation on n-Type Ge Junctionless FinFETs With Metal–Interlayer–Semiconductor Source/Drain Contact Structure

Jung

2019

IEEE J. Electron Devices Soc.

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“…Also, the fluctuation of threshold voltage with the radius of the silicon nanowire is significant in JL devices. The variability of SCEs parameters with respect to the physical parameters of the device is also high due to the random dopant fluctuation (RDF) [9][10][11][12].…”

Section: Introductionmentioning

confidence: 99%

Comparative analysis of gate-oxide engineering in charge plasma based nanowire transistor

Debnath,

Sikder,

Singha

2023

Eng. Res. Express

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In this work, a Hetero-Gate-Oxide Charge Plasma-based Nanowire Transistor (HGO-CPNWT) has been proposed, characterized, and a comparative analysis with the Conventional Charge Plasma-based Nanowire Transistor (CCPNWT) and the Stack-Gate-Oxide CPNWT (SGO-CPNWT) has been investigated. The effects of stacking a high-κ gate oxide with a low-κ gate oxide beneath the gate and segmenting the gate oxide with a high-κ oxide at the source side and low-κ oxide at the drain side have been analyzed with the short channel effects (SCEs) parameters and radio-frequency (RF) / analog figure of merits have been analyzed. The HGO-CPNWT demonstrates enhanced performances in terms of Ion/Ioff of 1.66×108, subthreshold slope (SS) of 65.74 mV/decade, drain induced barrier lowering (DIBL) of 47.857 mV/V, peak transconductance (gm) of 3.43×10-5 S/μm, and peak cut-off frequency (ft) of 114 GHz. The simulation employs a comprehensive quantum transport model (NEGF), and the comparative impacts of adjusting channel length (Lg), nanowire radius (r), and gate oxide thickness (Tox) are studied.

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“…There have been several quantum-mechanical statistical simulations in the past that aimed at assessing the impact of Random Discrete Dopants (RDD) on the variability of different figures of merit of JLFETs [3][4][5]. However, all these studies were conducted at low source-to-drain bias and considering only few tens of samples.…”

Section: Introductionmentioning

confidence: 99%

Quantum Transport Investigation of Threshold Voltage Variability in Sub-10 nm JunctionlessSi Nanowire FETs

Berrada

Lee

Carrillo-Nuñez

et al. 2018

2018 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD)

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In this paper, we use the Non-Equilibrium Green's Function formalism to study the dependence of the threshold voltage variability on the cross-section shape and the gate length in JunctionLess Field Effect Transistors. Each configuration, i.e. gate length and cross-section, was investigated using a statistical ensemble of 100 samples. We found that the variability in threshold voltage is increased independently of the cross-section shape when the gate length is shrunk down to 5 nm. We attribute this results to the higher wave function "randomization" in longer gate lengths.

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Random dopant fluctuations and statistical variability in n-channel junctionless FETs

Cited by 12 publications

References 32 publications

Impact of Random Dopant Fluctuation on n-Type Ge Junctionless FinFETs With Metal–Interlayer–Semiconductor Source/Drain Contact Structure

Impact of Random Dopant Fluctuation on n-Type Ge Junctionless FinFETs With Metal–Interlayer–Semiconductor Source/Drain Contact Structure

Comparative analysis of gate-oxide engineering in charge plasma based nanowire transistor

Quantum Transport Investigation of Threshold Voltage Variability in Sub-10 nm JunctionlessSi Nanowire FETs

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