Analytical model for TDDB-based performance degradation in combinational logic

Choudhury,; Chandra,; Mohanram,; Aitken,

doi:10.1109/date.2010.5457168

Cited by 38 publications

(19 citation statements)

References 14 publications

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“…For a given K, whatever the stress voltage value, the static current is limited and a plateau is observed. This is in agreement with the fact that the BD is more likely to be soft as it has already been observed [3,14]. It could be explained by the fact that the broken transistor is driven by other transistor, and even when stressed, the current is limited, so the BD remains soft, as already discussed [5].…”

Section: Soft Breakdown In Logic Gatessupporting

confidence: 89%

See 1 more Smart Citation

Impact of gate oxide breakdown in logic gates from 28nm FDSOI CMOS technology

Saliva¹,

Cacho²,

Ndiaye³

et al. 2015

2015 IEEE International Reliability Physics Symposium

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For advanced CMOS nodes, high performance is reached with the down scaling of both critical gate length and dielectrics stack. The aggressive reduction of dielectric thickness leads to a reduction of reliability margin due to breakdown. However, the first breakdown (BD) event does not always cause a functional failure in digital circuits. Lifetime extension based on device level parameters drift is difficult to handle, an accurate BD model is thus mandatory for predictive simulations at circuit level. Two dedicated test structures have been designed to track BD events impact on logic gates. Different AC-DC conditions are examined to be closer to operating conditions of digital circuits. Then a compact model for BD in logic gates is proposed: according to device level measurements, different severities of the BD event impact can be selected. Next Monte Carlo simulations are performed and enable to discuss the real impact of BD on logic gates in comparison with the measurements. In this way the measurements at device and circuit levels can be linked and the most likely post-BD device characteristics are highlighted. Therefore, the real impact of hard BD can be mitigated.

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Section: Soft Breakdown In Logic Gatessupporting

confidence: 89%

“…The localization in the overlap (drain or source) is a worse case from a BD impact point of view [13]. A power-law leakage current can be used [14]:…”

Section: Soft Breakdown In Logic Gatesmentioning

confidence: 99%

Impact of gate oxide breakdown in logic gates from 28nm FDSOI CMOS technology

Saliva¹,

Cacho²,

Ndiaye³

et al. 2015

2015 IEEE International Reliability Physics Symposium

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show abstract

“…As the severity of aging mechanisms depends on the technology under evaluation, the degradation applied in this work considered a maximum V th impact of 50 mV for NBTI and HCE effects, and a range of breakdown resistance from GO (fresh device) to KO (maximum degraded device) for TDDB effect. The behavior of each mechanism follows the ones already reported in the literature [7][8][9][10][11][12][13][14].…”

Section: Simulation Resultsmentioning

confidence: 82%

“…This conducting path is caused by a large electric field in the transistor gate oxide that eventually generates traps in the oxide, leading to tunneling currents. Once enough traps are created, they start affecting the electrical properties of the device, mainly the gate tunneling current [14]. A power law degradation model is usually applied to model the TBBD degradation [13].…”

Section: Tddbmentioning

confidence: 99%

Design of CMOS logic gates with enhanced robustness against aging degradation

Butzen¹,

Dal²,

Reis³

et al. 2012

Microelectronics Reliability

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“…Electro-migration specifies a force, introduced by the high current density, that can dislocate interconnect material at elevated temperatures, resulting in a total connection-loss. Time dependent dielectricity breakdown (TDDB) may occur in oxides, having collected a vast number of trapped oxide charges, forming a conductive path through the oxide and thus to a permanent device failure [3]. Finally, there are radiation induced permanent failures like single event latchup (SEL) and others, each of which finally leads to a thermal destruction of a device as a result of ionizing radiation.…”

Section: Introductionmentioning

confidence: 99%

Efficient NBTI modeling technique considering recovery effects

Eilers

Metzdorf

Helms

et al. 2014

Proceedings of the 2014 International Symposium on Low Power Electronics and Design

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The aging effect "Negative Bias Temperature Instability", which is highly dependent on device history, has a direct impact on the design of integrated circuits. In order to make realistic predictions available in the design process, simulation durations of existing history aware models must be significantly reduced. Therefore, a performance-oriented, yet accurate abstraction of the switching trap NBTI model is presented within this paper. Evaluation results for various stress scenarios demonstrate very precise NBTI simulations and a major improvement to another performance-oriented model abstraction. Simulation durations facilitate realistic aging predictions of larger components in a reasonable period of time.

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Analytical model for TDDB-based performance degradation in combinational logic

Cited by 38 publications

References 14 publications

Impact of gate oxide breakdown in logic gates from 28nm FDSOI CMOS technology

Impact of gate oxide breakdown in logic gates from 28nm FDSOI CMOS technology

Design of CMOS logic gates with enhanced robustness against aging degradation

Efficient NBTI modeling technique considering recovery effects

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