2013
DOI: 10.1108/compel-03-2013-0101
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Analytical modeling of quantization effects in surrounding-gate MOSFETs

Abstract: Purpose – The purpose of this paper is to present an analytical model and simulation for cylindrical gate all around MOSFTEs including quantum effects. Design/methodology/approach – To incorporating the impact of quantum effects, the authors have used variational method for solving the Poisson and Schrodinger equations. The accuracy of the results obtained using this model is verified by comparing them with simulation results. … Show more

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Cited by 10 publications
(5 citation statements)
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“…The analytical expression for surface potential in the silicon film is obtained by rigorously solving Poisson's equation [20] and is given by, ( )…”
Section: Surface Potential Modelmentioning
confidence: 99%
“…The analytical expression for surface potential in the silicon film is obtained by rigorously solving Poisson's equation [20] and is given by, ( )…”
Section: Surface Potential Modelmentioning
confidence: 99%
“…However, it has been widely confirmed that, the performances of these components are prone to be affected by parasitic parameters such as inter-electrode capacitance and resistance (Allagui et al , 2021), and prone to be affected by parameter drift phenomenon, which is in direct contact with some dynamic characteristics of MOSFETs (Chen et al , 2020; Mukunoki et al , 2018a, 2018b), Miller plateau and oscillations at the turn on/off moments, to name a few. Therefore, a reasonable and accurate model has a pivotal role in the performance analysis of both MOSFETs and circuit systems with such components (Palanichamy and Balamurugan, 2014; Mayilsamy et al , 2021; Hsu et al , 2020).…”
Section: Introductionmentioning
confidence: 99%
“…Reducing the channel length eventually gave rise to numerous limitations called shortchannel effects and decaying parasitic effects [2]. In the recent times, we have faced a problem called latch-up; this is a drawback of the CMOS technology used for manufacturing conventional MOSFETs [3]. A new fabrication process named SOI technology which reduces latch-up by creating a physical barrier between p-n-p-n junction, reducing parasitic effects.…”
Section: Introductionmentioning
confidence: 99%