Analytical Modeling of the SMART NoC

Bhattacharya, Debajit; Jha, Niraj K.

doi:10.1109/tmscs.2017.2704101

Cited by 5 publications

(4 citation statements)

References 38 publications

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“…The obtained results show that the number of virtual channels and flits contention are inversely proportional; besides it, the authors cannot demonstrate the influence of buffers size in packet latency. Comparing the simulations results with predictions, the accuracy was superior to 85% in all scenarios [18].…”

Section: Analytical Modelsmentioning

confidence: 90%

An investigation of latency prediction for NoC-based communication architectures using machine learning techniques

et al. 2019

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Due to the increasing number of cores in Systems on Chip (SoCs), bus architectures have suffered with limitations regarding performance. As applications demand higher bandwidth and lower latencies, buses have not been able to comply with such requirements due to longer wires and increased capacitance. Facing this scenario, Networks-on-Chip (NoCs) emerged as a way to overcome the limitations found in bus-based systems. Fully exploring all possible NoC characteristics settings is unfeasible due to the vast design space to cover. Therefore, some methods which aim to speed up the design process are needed. In this work, we propose the use of machine learning techniques to optimise NoC architecture components during the design phase. We have investigated the performance of several different ML techniques and selected the Random Forest one targeting audio/video applications. The results have shown an accuracy of up to 90% and 85% for prediction involving arbitration and routing protocols, respectively, and in terms of applications inference, audio/video achieved up to 99%. After this step, we have evaluated other classifiers for each application individually, aiming at finding the adequate one for each situation. The best class of classifiers found was the Tree-based one (Random Forest, Random Tree, and M5P) which is very encouraging and it points to different approaches from the current state of the art for NoCs latency prediction.

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Section: Analytical Modelsmentioning

confidence: 90%

An investigation of latency prediction for NoC-based communication architectures using machine learning techniques

et al. 2019

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“…Bhattacharya et al [15], introduced an analytical methodology for assessing the performance of a cutting-edge NoC design. In this NoC, packets can bypass routers partially or completely as they travel from source to destination.…”

Section: Related Workmentioning

confidence: 99%

“…Adjusting multiple parameters in the Network-on-Chip (NoC) design significantly impacts its performance. These parameters encompass the quantity of virtual channels (VCs) within each virtual network (Vnet), the dimensions of flits, and the depth of the NoC buffers [15]. Reducing the number of VCs per Vnet gives rise to heightened contention among flits, consequently leading to an increase in latency.…”

Section: Network-on-chip Configurationmentioning

confidence: 99%

Simultaneous Optimization of Network-on-Chip for Improved Reliability and Reduced Average Packet Latency Considering Buffer Size Constraints

Abdolhosseini,

Zarandi

2024

Preprint

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Managing the complex interconnections found in contemporary chip designs is achievable through the utilization of network-on-chip (NoC) architectures. Optimizing NoC configuration is critical for balancing reliability and latency. This paper presents a study on simultaneously optimizing NoC to improve reliability and reduce average packet latency, while considering buffer size constraints. Buffer size significantly impacts latency, cost, and reliability, making it a key element for optimization. To validate latency estimates, we compared against the Garnet2.0 simulator. Optimization utilized the NSGA-II algorithm to concurrently optimize multiple objectives like reliability and latency. The buffer size in NoC input ports constrained optimization. MATLAB was selected for implementing the algorithm due to its optimization libraries and user-friendly interface. We provide extensive findings for different NoC dimensions when subjected to both uniform and hot-spot traffic. This study contributes to designing robust, efficient on-chip communication, which is essential as computing systems demand increases.

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“…SOC system is a thought for on chip circuit with the goal of increasing the demand for parallel processing by enhanced the performance and productivity of a chip design. As a result, chip multiprocessing (CMP) system has undergone a revolution [3]. Instead, NoC connectivity has developed as a significant on-chip communication option.…”

Section: Introductionmentioning

confidence: 99%

Design and implementation 4x4 Network on Chip (NoC) using FPGA

Al-Azzwai¹,

Al-Hilali²,

Jumma³

2022

PEN

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Network on Chip is one of the most crucial in the development of the networks and routers in new days due to the improvement that make through way of sending huge packets of data and technology and protocol that used for sending the packets between IP cores. Also, the NoC is removed the old ways of technique and protocols of sending packets through routers. The NoC is the most enhanced and efficient in working in parallel ways. Hence, Field Program Gate Array (FPGA) is used in the designing of router that its architecture depending on the NoC. The research proposed in this paper proposed 4x4 nodes router with mesh network that support two-dimensional architecture. A real time test is used for experimental through FPGA and the test verified efficient packets transporting via two array buffers that integrated in the proposed router architecture.

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Analytical Modeling of the SMART NoC

Cited by 5 publications

References 38 publications

An investigation of latency prediction for NoC-based communication architectures using machine learning techniques

An investigation of latency prediction for NoC-based communication architectures using machine learning techniques

Simultaneous Optimization of Network-on-Chip for Improved Reliability and Reduced Average Packet Latency Considering Buffer Size Constraints

Design and implementation 4x4 Network on Chip (NoC) using FPGA

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