Analytical modelling and simulation of single-gate SOI TFET for low-power applications

Samuel, T. S. Arun; Balamurugan, N. B.; Bhuvaneswari, S.; Sharmila, D.; Padmapriya, K.

doi:10.1080/00207217.2013.796544

Cited by 40 publications

(27 citation statements)

References 14 publications

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“…The Comparative drain current analyses of Single gate Silicon on insulator (SOI) TFET [9] and DMDG TFET are shown in Fig. 8.…”

Section: Resultsmentioning

confidence: 99%

“…The potential profile in the vertical direction is assumed to be a second-order polynomial [9], i.e., …”

Section: Surface Potentialmentioning

confidence: 99%

“…TFET is a promising device to replace the conventional MOSFET for low power applications [8]. The applications of TFETs includes implementation on digital circuits like NAND, NOR and in six transistor SRAM memory cell [9].…”

Section: Introductionmentioning

confidence: 99%

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An Analytical Modeling and Simulation of Dual Material Double Gate Tunnel Field Effect Transistor for Low Power Applications

Samuel¹,

Balamurugan²

2014

Journal of Electrical Engineering and Technology

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-In this paper, a new two dimensional (2D) analytical modeling and simulation for a Dual Material Double Gate tunnel field effect transistor (DMDG TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunnelling generation rate and thus we numerically extract the tunnelling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.

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“…The Comparative drain current analyses of Single gate Silicon on insulator (SOI) TFET [9] and DMDG TFET are shown in Fig. 8.…”

Section: Resultsmentioning

confidence: 99%

“…The potential profile in the vertical direction is assumed to be a second-order polynomial [9], i.e., …”

Section: Surface Potentialmentioning

confidence: 99%

See 1 more Smart Citation

An Analytical Modeling and Simulation of Dual Material Double Gate Tunnel Field Effect Transistor for Low Power Applications

Samuel¹,

Balamurugan²

2014

Journal of Electrical Engineering and Technology

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“…Unfortunately, a conventional bulk-based 6T SRAM cell faces several challenges and cannot operate successfully at low supply voltages (Pasandi & Fakhraie, 2013b). By using new technologies, such as FinFET, SOI, 3D designs, nano computing and so on that help mitigate these drawbacks at low supply voltages, is a very attractive area in research but it is very expensive, pushing back the huge investment that exists in the current CMOS technology (Samuel, Balamurugan, Bhuvaneswari, Sharmila, & Padmapriya, 2013). Thus, this necessitates proposing new structures for SRAM cells that are based on traditional technologies and can also address the disadvantages at low supply voltages.…”

Section: Introductionmentioning

confidence: 99%

A new low-power 10T SRAM cell with improved read SNM

Pasandi

Jafari

Imani

2015

International Journal of Electronics

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This paper describes the characteristics of a new 10T structure for SRAM cell that works quite well in the sub-threshold region. This new architecture has good characteristics in write and read delay and energy compared with other new structures. This new 10T topology improves read static noise margin (SNM) and write operation speed with respect to other topologies in the same or even lower power consumption. The new topology has at least 13% lower power consumption compared with the best of recent architectures. Its write characteristics also are similar to those of 6T-SRAM, which has improved write delay and energy. The new 10T SRAM cell also consumes lower power compared with other cells. The stacking is used to suppress the standby leakage through the read path. The simulations were performed using HSPICE 2011 in a 16 nm bulk CMOS Berkeley predictive technology model (BPTM).

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“…Owing to its extremely low off-state current, the turnon characteristic of TFET would be superior to MOSFET. Therefore, TFET devices can be recognized as one of the most possible candidates of MOSFETs [4][5][6][7][8][9]. However, TFET has a drawback of low on-state current ( on ).…”

Section: Introductionmentioning

confidence: 99%

Impact of Interface Traps on Direct and Alternating Current in Tunneling Field-Effect Transistors

Zhi

Zhang

et al. 2015

Journal of Electrical and Computer Engineering

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We demonstrate the impact of semiconductor/oxide interface traps (ITs) on the DC and AC characteristics of tunnel field-effect transistors (TFETs). Using the Sentaurus simulation tools, we show the impacts of trap density distribution and trap type on the n-type double gate-(DG-) TFET. The results show that the donor-type and acceptor-type ITs have the great influence on DC characteristic at midgap. Donor-like and acceptor-like ITs have different mechanism of the turn-on characteristics. The flat band shift changes obviously and differently in the AC analysis, which results in contrast of peak shift of Miller capacitor gd for n-type TFETs with donor-like and acceptor-like ITs.

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Analytical modelling and simulation of single-gate SOI TFET for low-power applications

Cited by 40 publications

References 14 publications

An Analytical Modeling and Simulation of Dual Material Double Gate Tunnel Field Effect Transistor for Low Power Applications

An Analytical Modeling and Simulation of Dual Material Double Gate Tunnel Field Effect Transistor for Low Power Applications

A new low-power 10T SRAM cell with improved read SNM

Impact of Interface Traps on Direct and Alternating Current in Tunneling Field-Effect Transistors

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