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Surrounding gate architecture for transistors has been shown to alleviate many of the problems posted by scaling and short channel effects. Semiconducting nanowires have recently attracted considerable attention in the semiconductor industry. With their unique electrical and optical properties, they offer interesting perspectives for basic research as well as for technology. In this paper, we have proposed a new analytical model for three different geometries of Surrounding Gate Silicon Nanowire Transistors. I–V characteristics (current-voltage) of the devices are effectively derived in all the three regions of operation. The variation of threshold voltage and drain current due to the device parameters like silicon thickness, doping concentration and radius are also predicted. Effectiveness of the models are fully validated by comparing the analytical results with the TCAD simulation results.

-In this paper, a new two dimensional (2D) analytical modeling and simulation for a Dual Material Double Gate tunnel field effect transistor (DMDG TFET) is proposed. The Parabolic approximation technique is used to solve the 2-D Poisson equation with suitable boundary conditions and analytical expressions for surface potential and electric field are derived. This electric field distribution is further used to calculate the tunnelling generation rate and thus we numerically extract the tunnelling current. The results show a significant improvement in on-current characteristics while short channel effects are greatly reduced. Effectiveness of the proposed model has been confirmed by comparing the analytical results with the TCAD simulation results.