Analytical Percolation Model for Predicting Anomalous Charge Loss in Flash Memories

Degraeve, R.; Schuler, F.; Kaczer, B.; Lorenzini, Marilinda; Wellekens, D.; Hendrickx, Paul; Duuren, M. van; Dormans, G. J. M.; Houdt, J. Van; Haspeslagh, L.; Groeseneken, G.; Tempel, G.

doi:10.1109/ted.2004.833583

Cited by 83 publications

(63 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Precycle retention loss increases for Si + SiN due to shallower electron traps, as explained in [30]. Based on FG flash results [29], [35], it is expected that stress-induced leakage current (SILC) due to trap generation in TO will result in higher retention loss after cycling. However, it is interesting to note that N + SiN stacks show similar charge loss, whereas Si + SiN stacks exhibit improvement in charge retention characteristics (similar to published results [24]) after cycling.…”

Section: E Postcycling Retentionmentioning

confidence: 97%

Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) Operation

Sandhya

Oak

Chattar

et al. 2010

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

Abstract-Program/Erase (P/E) cycling endurance in poly-Si/Al 2 O 3 /SiN/SiO 2 /Si (SANOS) memories is systematically studied. Cycling-induced trap generation, memory window (MW) closure, and eventual stack breakdown are shown to be strongly influenced by the material composition of the silicon nitride (SiN) charge trap layer. P/E pulsewidth and amplitude, as well as starting program and erase flatband voltage (V FB ) levels (therefore the overall MW), are shown to uniquely impact stack degradation and breakdown. An electron-flux-driven anode hole generation model is proposed, and trap generation in both SiN and tunnel oxide are used to explain stack degradation and breakdown. This paper emphasizes the importance of SiN layer optimization for reliably sustaining large MW during P/E operation of SANOS memories.

show abstract

Section: E Postcycling Retentionmentioning

confidence: 97%

Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) Operation

Sandhya

Oak

Chattar

et al. 2010

IEEE Trans. Electron Devices

View full text Add to dashboard Cite

show abstract

“…As the flash cell wears out with increasing P/E cycles, the amount of trapped charge also increases [19], and so does the TAT effect. At high P/E cycles, the amount of trapped charge is large enough to form percolation paths that will significantly hamper the insulating properties of the gate dielectric [18], resulting in retention failure.…”

Section: Trap-assisted Tunneling (Tat)mentioning

confidence: 99%

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

Cai

Luo

Haratsch³

et al. 2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

235

267

View full text Add to dashboard Cite

Abstract-Retention errors, caused by charge leakage over time, are the dominant source of flash memory errors. Understanding, characterizing, and reducing retention errors can significantly improve NAND flash memory reliability and endurance. In this paper, we first characterize, with real 2y-nm MLC NAND flash chips, how the threshold voltage distribution of flash memory changes with different retention age -the length of time since a flash cell was programmed. We observe from our characterization results that 1) the optimal read reference voltage of a flash cell, using which the data can be read with the lowest raw bit error rate (RBER), systematically changes with its retention age, and 2) different regions of flash memory can have different retention ages, and hence different optimal read reference voltages. Based on our findings, we propose two new techniques. First, Retention Optimized Reading (ROR) adaptively learns and applies the optimal read reference voltage for each flash memory block online. The key idea of ROR is to periodically learn a tight upper bound, and from there approach the optimal read reference voltage. Our evaluations show that ROR can extend flash memory lifetime by 64% and reduce average error correction latency by 10.1%, with only 768 KB storage overhead in flash memory for a 512 GB flash-based SSD. Second, Retention Failure Recovery (RFR) recovers data with uncorrectable errors offline by identifying and probabilistically correcting flash cells with retention errors. Our evaluation shows that RFR reduces RBER by 50%, which essentially doubles the error correction capability, and thus can effectively recover data from otherwise uncorrectable flash errors.

show abstract

“…With high field stress used for programming, properties of the insulating layers are degraded. SILC seems to be due to some Trap-Assisted Tunneling effect (TAT) [12]. Multiple models have been developed to describe the SILC phenomenon.…”

Section: Cell Reliability Modelingmentioning

confidence: 99%

“…Multiple models have been developed to describe the SILC phenomenon. The percolation model [12] seems a good way to explain the underlying physical phenomenon.…”

Section: Cell Reliability Modelingmentioning

confidence: 99%

Evaluation of Design for Reliability Techniques in Embedded Flash Memories

Godard¹,

Daga²,

Торрес³

et al. 2007

2007 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

View full text Add to dashboard Cite

show abstract

Analytical Percolation Model for Predicting Anomalous Charge Loss in Flash Memories

Cited by 83 publications

References 12 publications

Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) Operation

Study of P/E Cycling Endurance Induced Degradation in SANOS Memories Under NAND (FN/FN) Operation

Data retention in MLC NAND flash memory: Characterization, optimization, and recovery

Evaluation of Design for Reliability Techniques in Embedded Flash Memories

Contact Info

Product

Resources

About