Analytical transient response and propagation delay evaluation of the CMOS inverter for short-channel devices

Analytical transient response and propagation delay model for nanoscale CMOS inverter

“…A circuit's speed/frequency and dynamic power dissipation are both affected significantly by propagation delay, and hence timing analysis has been investigated for several decades [1][2][3][4][5][6][7]. With the increasing complexity of modern very large scale integration (VLSI) systems, transistor level simulation consumes much more computation time because of the nonlinear transfer characteristics of CMOS gates [8][9][10]. Therefore, an analytical delay model that does not need numerical iterations is needed to extract delay efficiently, and much work has been published on the topic [3,[6][7][8][9][10][11][12][13][14][15][16][17][18][19].…”

“…With the increasing complexity of modern very large scale integration (VLSI) systems, transistor level simulation consumes much more computation time because of the nonlinear transfer characteristics of CMOS gates [8][9][10]. Therefore, an analytical delay model that does not need numerical iterations is needed to extract delay efficiently, and much work has been published on the topic [3,[6][7][8][9][10][11][12][13][14][15][16][17][18][19].For extracting the propagation delay, development of a delay model for a CMOS inverter is considered as the first step [14], and a number of inverter delay models have been developed [6][7][8][9][10][11][12][13][14][15]. The first inverter delay expression was introduced by Burns [1].…”

Characterization of Normal Propagation Delay for Delay Degradation Model (DDM)

“…Actually, characterizing the DDM completely also implies the characterization of the normal propagation delay (t p0 ), and the value of t p0 depends on both C L and τ in [1,4]. Our main objective is to analyse the behaviour of t p0 in order to implement it, as part of DDM, in a logic timing simulator (HALOTIS) focused on the simulation of circuits based on standard cell libraries.…”

“…In the specialized literature there are different papers [1,2] where authors present accurate normal delay models and it would be possible to select one of these models to provide a normal propagation delay model for the DDM, though, since they are models focused on the geometric level, they are not suited to our aims.…”

“…In the field of logic simulation of digital CMOS circuits, delay models exist that take into account most issues affecting accuracy [1][2][3][4]: low voltage, submicron and deep submicron devices, transition waveform, etc. There are also dynamic effects, the most important being the so-called input collisions [5], which happens when two or more input signals change almost simultaneously.…”