In a preceding paper, the effect of the epitaxial silicon growth process on impurity distribution in the epitaxial film was treated in terms of a countercurrent model, and experimental results were presented for n-type films on n-type substrates. In the present paper, additional experimental data are presented for p-on-p, n-on-p, and p-on-n growth conditions.For n-on-p, or p-on-n growth, the electrical junctions are shifted by the process a distance of xj microns (the junction lag) from the substrate-film interface. The process-dominated junction lag may be much larger than that predicted from diffusion considerations. It is dependent on the film growth temerature and the doping levels in the substrate and in the gas phase. As predicted by the countercurrent distribution expression, it is greater for lower growth temperatures.Junction lags from immeasurably small values up to greater than 30~ have been generated. There is quantitative agreement between the observed magnitude of the junction lag and the value predicted by use of the countercurrent distribution expression. Also, for those samples measured electrically (with junction lags of 1.8-4.8~) the agreement between the measured mean impurity concentration level (by four-point probe measurements) in the epitaxial layer and the mean impurity level predicted on the basis of the distribution expression is quantitative.