2006
DOI: 10.1109/tdmr.2006.881461
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Anomalous Reduction of Hot-Carrier-Induced On-Resistance Degradation in n-Type DEMOS Transistors

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Cited by 20 publications
(11 citation statements)
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“…So the hot carrier degradation in LEDMOS is more susceptible to the variety of Vgs than that of Vds. At low Vgs, hot hole injection and electron injection occur simultaneously in the nLEDMOS, which is different from the results in [5][6][7]. At high Vgs, hole injection decreases and electron injection becomes the main cause for the degradation.…”
Section: Introductioncontrasting
confidence: 57%
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“…So the hot carrier degradation in LEDMOS is more susceptible to the variety of Vgs than that of Vds. At low Vgs, hot hole injection and electron injection occur simultaneously in the nLEDMOS, which is different from the results in [5][6][7]. At high Vgs, hole injection decreases and electron injection becomes the main cause for the degradation.…”
Section: Introductioncontrasting
confidence: 57%
“…We demonstrate that a new electron and hole injection mechanism occurs under different stress conditions and give evidence of injection and trapping of hot electron in the gate oxide and hot hole in the field oxide, which leads to degradation of the electrical parameters and is different from the results in [7]. At low Vgs, the degradation mechanism affecting hot carrier effect was due to both hot-hole injection in the field oxide and hot-electron injection in the gate oxide, and at high Vgs hole injection decreases and the electron injection becomes dominant, which is different from the results in [5][6][7]. With the stress time increasing the hot carrier injection will reach saturation and the interface trap formation in the channel region takes over.…”
Section: Introductionmentioning
confidence: 63%
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“…Recently, hot-carrier reliability of n-type DEMOS and LDMOS devices has been studied. [1][2][3][4][5][6] However, much less effort is done to address the reliability of p-type high-voltage transistors. 7) In this paper, hot-carrier reliability of p-type DEMOS devices is investigated.…”
Section: Introductionmentioning
confidence: 99%
“…Figure 4 shows the simulated vertical electric field along the Si/SiO 2 interface for the device biased under V ds ¼ 13:2 V and V gs ¼ 6 V. It is clear that there is a sign change in vertical electric field between channel and N À drift region. 11) The sign change in vertical electric field indicates that the type of hot carriers (electrons or holes) injected toward the gate oxide is location dependent. This argument can be confirmed from the results shown in Fig.…”
Section: Resultsmentioning
confidence: 99%