APF pitch-halving for 22nm logic cells using gridded design rules

Abstract

The 22nm logic technology node with dimensions of ~32nm will be the first node to require some form of pitch-halving. A unique combination of a Producer APF®-based process sequence and GDR-based design style permits implementation of random logic functions with regular layout patterns. The APF (Advanced Patterning Film) pitchhalving approach is a classic Self-Aligned Double Patterning scheme (SADP) [1,2,3,4] which involves the creation of CVD dielectric spacers on an APF sacrificial template and using the spacers as a hardmask for line frequency doubling. The Tela Canvas™ implements Gridded Design Rules (GDR) using straight lines placed on a regular grid. Logic functions can be implemented using lines on a half-pitch with gaps at selected locations.

32nm and below logic patterning using optimized illumination and double patterning

“…If tight fin pitch is required, a line process like SADP can be used. [11] The Gate layer will become more challenging, with a line pitch of 84nm and cut widths of 36nm. The line pattern can still be handled by a single pass of dipole illumination at NA=1.35; since the pitch is dictated by the contact-to-gate space, the line width and space can be patterned at 1:1 then trimmed to the desired final size.…”

“…The line pattern can be created by techniques like SADP which allows patterning at twice the final pitch, then using sidewall spaces to double the spatial frequency. [11] An approach like SADP is suitable for either a subtractive-etch Metal-1 process or a single Damascene trench process.…”

Improved mask-based CD uniformity for gridded-design-rule lithography

“…An additional benefit is the high RET performance of linear polarization, that is both adequate for the 1D pattern, and is simplest to implement [11]. Also, the regular design practically lends itself to double patterning lithography, either through a "lithoetch-litho-etch" approach, where pattern splitting is greatly facilitated [8], or through a spacer technique, as was recently demonstrated [12]. Last, the simplification is carried onto the layers of contact holes, that are also snapped to a grid because of the gridded nature of the gate and metal (1 & 2) layers.…”

“…This may be used in case the number of possible (or suspected) mask error sources is larger (e.g., in order to account for haze). Or, alternatively, one may get an over-determined set of coupled equations (12), and then increase robustness of solution (to noise, e.g.) through least-mean square solution.…”

“…measured, and partial derivatives of av I per error source and per EC computed, eqs (12). can be solved for the unknown mask error sources…”