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The Intel 45nm Penryn™ CPU was a landmark design, not only for its implementation of high-K metal gate materials 1 , but also for the adoption of a nearly gridded design rule (GDR) layout architecture for the poly silicon gate layer 2 . One key advantage of using gridded design rules is reduction of design rules and ease of 1-dimensional scaling compared to complex random 2-dimensional layouts. In this paper, we demonstrate the scaling capability of GDR to 16nm and 22nm logic nodes. Copying the design of published images for the Intel 45nm Penryn™ poly-silicon layer 2 , we created a mask set designed to duplicate those patterns targeting a final pitch of 64nm and 52nm using Sidewall Spacer Double Patterning for the extreme pitch shrinking and performed exploratory work at final pitch of 44nm. Mask sets were made in both tones to enable demonstration of both damascene (dark field) patterning and poly-silicon gate layer (clear field) GDR layouts, although the results discussed focus primarily on poly-silicon gate layer scaling.The paper discusses the line-and-cut double patterning technique for generating GDR structures, the use of sidewall spacer double patterning for scaling parallel lines and the lithographic process window (CD and alignment) for applying cut masks. Through the demonstration, we highlight process margin issues and suggest corrective actions to be implemented in future demonstrations and more advanced studies. Overall, the process window is quite large and the technique has strong manufacturing possibilities.

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The 22nm logic technology node with dimensions of ~32nm will be the first node to require some form of pitch-halving. A unique combination of a Producer APF®-based process sequence and GDR-based design style permits implementation of random logic functions with regular layout patterns. The APF (Advanced Patterning Film) pitchhalving approach is a classic Self-Aligned Double Patterning scheme (SADP) [1,2,3,4] which involves the creation of CVD dielectric spacers on an APF sacrificial template and using the spacers as a hardmask for line frequency doubling. The Tela Canvas™ implements Gridded Design Rules (GDR) using straight lines placed on a regular grid. Logic functions can be implemented using lines on a half-pitch with gaps at selected locations.

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