Application decomposition for high-speed network processing platforms

A novel network processor for security applications in high-speed data networks

“…The PRO3 architecture is based on a high-performance RISC core, which is extended with programmable, pipelined hardware. Real-time protocol functions and functions that place heavy demands on the central processing unit (CPU) are handled by the programmable hardware; the remaining functions-as well as higher-layer protocols-are handled by a pair of on-chip RISCprocessor-based modules optimized for fast contextswitching and pipelined processing [17]. With this architecture, it is expected that significant performance improvements will be achieved in: • The rate of connection insertion and deletion, which measures the number of connections per second supported by the system when applications set up and tear down connections continuously; • The throughput, which measures the aggregate number of bytes per packet that the system can process and forward to its output interface; • The latency, which measures the aggregate delay encountered by network traffic, and which is introduced by the processing delay of the system; and • The number of processed sessions, which measures the maximum number of simultaneous connections supported by the system.…”

Processing and scheduling components in an innovative network processor architecture

“…For the performance evaluation of the programmable units firmware for all the microengines was developed and open source C code was ported for implementing a stateful inspection Firewall with Network Address Translation (NAT) support [5]. Samples of real TCP/IP traffic have been used as input in H/W simulation and the processing time in each module was measured.…”

Software processing performance in network processors

“…The common high speed path (up to the transport layer) is performed in the PRO3 hardware pipeline, and higher layer applications on the internal Hyperstone RISC CPU. Packets are stored per-flow in the external DRAM in queues implemented as linked list data structures [2] and can be retrieved by the Data Memory Manager module (DMM)0 in response to specific commands. The packets are then delivered over the internal bus either to a) the RPM modules or b) the control RISC CPU or c) a host CPU (via the insert/extract interface) or d) the output interface.…”