Application-directed voltage scaling

Abstract

Abstract-Clock (and voltage) scheduling is an important technique to reduce the energy consumption of processors that support voltage scaling. It is difficult, however, to achieve good results using only statistics from the operating system level when applications show bursty (unpredictable) behavior. We take the approach that such applications must be made power-aware and specify their average execution time (AET) and the deadline to the scheduler controlling the clock speed and processor voltage. This paper describes our energy priority scheduling (EPS) algorithm supporting power-aware applications. EPS orders tasks according to how tight their deadlines are and how often tasks overlap. Low-priority tasks are scheduled first, since they can be easily preempted to accommodate for high-priority tasks later. The EPS algorithm does not always yield the optimal schedule, but has a low complexity. We have implemented EPS on a StrongARM-based variable-voltage platform. We conducted experiments with a modified video decoder that estimates the AET of each frame. Measurements show that application-directed voltage scaling reduces processor power consumption with 50% for the bursty video decoder without missing any frame deadlines.Index Terms-Adaptive software, low power, power awareness, voltage scaling.

Adaptive-Buffer Power Save Mechanism for Mobile Multimedia Streaming

“…They argue that power related research in the area of wireless multimedia can be divided into two princi-pal categories: power-aware multimedia decoding, where the power save is implemented when the power level drops, such as in [40] and [41] and powerefficient radio communications where power-efficient methods are used from the outset, as in [42], [43] and [44]. The authors state that streaming applications typically transmit a constant stream of packets with periodic arrival times.…”

Chameleon: Application-Level Power Management

“…An online hardware approach for voltage and frequency control in multiple clock domain microprocessors has been proposed in [29]. OS-based approaches determine a system-wide CPU setting based on the processor demands of the currently active tasks [7,8,16,17,23]. In this approach, individual applications do not have any direct control over the CPU power settings.…”

Compiler-Driven Leakage Energy Reduction in Banked Register Files

“…Conversely, [22] presents other techniques that retain the idea of a centralized architecture, but the register file is split into interleaved banks, which reduces the total number of ports in each bank. In a more general context, [23] have proposed efficient voltage scaling techniques according to the application's behavior, which can efficiently reduce the overall power consumption of the system. However, in all these previous approaches it has not been studied how to apply similar techniques to multi-processor systems with shared register files by including a set of hardware extensions and power-aware compilation to control them, as we propose in this paper.…”