Compiler-Driven Leakage Energy Reduction in Banked Register Files

Atienza, David; Raghavan, Praveen; Ayala, José L.; Micheli, Giovanni De; Catthoor, Francky; Verkest, D.; López‐Vallejo, Marisa

doi:10.1007/11847083_11

Cited by 3 publications

(2 citation statements)

References 17 publications

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“…Atienza et al [10] are focused on DSP (Digital Signal Processing) and ASIP (Application-Specific Instruction-Set Processor) architectures, specially led to multimedia applications in embedded systems. The authors apply the DVS (Dynamic Voltage Scale) technique to change to low-power state the unused registers.…”

Section: Related Workmentioning

confidence: 99%

Evolutionary Design of the Memory Subsystem

Álvarez,

Risco-Martín,

Colmenar

2023

Preprint

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The memory hierarchy has a high impact on the performance and power consumption in the system. Moreover, current embedded systems, included in mobile devices, are specifically designed to run multimedia applications, which are memory intensive. This increases the pressure on the memory subsystem and affects the performance and energy consumption. In this regard, the thermal problems, performance degradation and high energy consumption, can cause irreversible damage to the devices.We address the optimization of the whole memory subsystem with three approaches integrated as a single methodology. Firstly, the thermal impact of register file is analyzed and optimized. Secondly, the cache memory is addressed by optimizing cache configuration according to running applications and improving both performance and power consumption. Finally, we simplify the design and evaluation process of general-purpose and customized dynamic memory manager, in the main memory. To this aim, we apply different evolutionary algorithms in combination with memory simulators and profiling tools. This

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Section: Related Workmentioning

confidence: 99%

Evolutionary Design of the Memory Subsystem

Álvarez,

Risco-Martín,

Colmenar

2023

Preprint

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“…This analysis will allow to define temperature-aware access policies that reduce the temperature of the device as well as the power consumption [15]. These experiments have been performed for every placement of the layout (positions 1, 2, 3 and 4) and three different access patterns (registers accessed from a bank placed on the right hand side of the register file, accessed registers randomly placed in several spots of the device and registers accessed in a homogeneous manner as a chess board).…”

Section: Optimization Policiesmentioning

confidence: 99%

Exploring Temperature-Aware Design of Memory Architectures in VLIW Systems

Ayala

Apavatjrut

Atienza

et al. 2007

Innovative Architecture for Future Generation High-Performance Processors and Systems (IWIA 2007)

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Temperature-aware register reallocation for register file power-density minimization

Zhou

Петров

2009

ACM Trans. Des. Autom. Electron. Syst.

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Increased chip temperature has been known to cause severe reliability problems and to significantly increase leakage power. The register file has been previously shown to exhibit the highest temperature compared to all other hardware components in a modern high-end embedded processor, which makes it particularly susceptible to faults and elevated leakage power. We show that this is mostly due to the highly clustered register file accesses where a set of few registers physically placed close to each other are accessed with very high frequency. We propose compile-time temperature-aware register reallocation methodologies for breaking such groups of registers and to uniformly distribute the accesses to the register file. This is achieved with no performance and no hardware overheads. We show that the underlying problem is NP-hard, and subsequently introduce and evaluate two efficient algorithmic heuristics. Our extensive experimental study demonstrates the efficiency of the proposed methodology. ACM Reference Format:Zhou, X., Yu, C., and Petrov, P. 2009. Temperature-aware register reallocation for register file power-density minimization.

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Compiler-Driven Leakage Energy Reduction in Banked Register Files

Cited by 3 publications

References 17 publications

Evolutionary Design of the Memory Subsystem

Evolutionary Design of the Memory Subsystem

Exploring Temperature-Aware Design of Memory Architectures in VLIW Systems

Temperature-aware register reallocation for register file power-density minimization

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