2021 58th ACM/IEEE Design Automation Conference (DAC) 2021
DOI: 10.1109/dac18074.2021.9586282
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Application of Deep Reinforcement Learning to Dynamic Verification of DRAM Designs

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Cited by 5 publications
(4 citation statements)
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“…The authors of [12] claim that, using RL, tests generated by their approach were able to achieve higher coverage values than a state-of-the-art test generator based on genetic algorithms presented in [16]. The study in [17] uses a training policy based on the k-nearest neighbor (K-NN) ML algorithm, approaching deep reinforcement learning (DRL) domain. The authors of [17] show how trained agents using RL mechanisms can achieve a higher coverage value compared with tests written by engineers, given operations performed on a DRAM memory.…”
Section: Related Workmentioning
confidence: 99%
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“…The authors of [12] claim that, using RL, tests generated by their approach were able to achieve higher coverage values than a state-of-the-art test generator based on genetic algorithms presented in [16]. The study in [17] uses a training policy based on the k-nearest neighbor (K-NN) ML algorithm, approaching deep reinforcement learning (DRL) domain. The authors of [17] show how trained agents using RL mechanisms can achieve a higher coverage value compared with tests written by engineers, given operations performed on a DRAM memory.…”
Section: Related Workmentioning
confidence: 99%
“…The study in [17] uses a training policy based on the k-nearest neighbor (K-NN) ML algorithm, approaching deep reinforcement learning (DRL) domain. The authors of [17] show how trained agents using RL mechanisms can achieve a higher coverage value compared with tests written by engineers, given operations performed on a DRAM memory. One example in [12] and the examples in [17] deal with memory-related verification.…”
Section: Related Workmentioning
confidence: 99%
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“…Most data in the semiconductor fields, however, is not available due to high measurement costs. Thus, data-driven approaches have been applied to limited applications such as chip design automation, 3) test vector generation, 4) process optimization, 5) and defect detection. 6,7) Such studies have something in common they can gather massive data, readily.…”
Section: Introductionmentioning
confidence: 99%