Application of Real-Time DEVS to Analysis of Safety-Critical Embedded Control Systems: Railroad Crossing Control Example

Abstract

This article presents an application of the Discrete Event System Specification (DEVS) framework to the design and safety analysis of a real-time embedded control system, a railroad crossing control system. The authors employ an extension of the DEVS formalism, real-time DEVS (RT-DEVS), which has a sound semantics for the specification of real-time systems in a hierarchical modular fashion. The notion of a clock matrix for communicating RT-DEVS models is proposed, which represents a global time between the models. Based on the composition rules and the clock matrix, an algorithm for the generation of a timed reachability tree is developed that can be used for safety analysis at two phases: an untimed and timed analysis phase. A railroad crossing control example demonstrates that the proposed analysis for RT-DEVS models would be effective to verify the safety property of real-time control systems.

A development methodology for embedded systems based on RT-DEVS

“…In particular, model checking activities rest on a translation of an RT-DEVS model onto the timed automata of Uppaal. All of this avoids the use of proprietary analysis tools as described in [25], and opens to the exploitation of efficient algorithms and data structures of the popular Uppaal toolbox [26]. Of course, in the case of large models which can be difficult to analyze with model checking, the approach depends on simulation.…”

“…The modelling language is RT-DEVS [15,25], i.e. a specialization of classic discrete event system specification (DEVS) [27] with a weak synchronous communication model and constructs for expressing timing constraints.…”

“…An application of RT-DEVS to safety analysis, called timed behavior analysis (TBA), is proposed in [25], where clock matrices are exploited for generating a timed reachability graph of a given model. The achieved graph is then explored for checking whether "unsafe" states can be reached.…”

“…Novel in the work described in this paper is: -a mapping of the fundamental phases of modelling and safety/temporal analysis of RT-DEVS systems in terms of the popular and efficient Uppaal toolbox with timed automata [4,8,12]. The translation purposely avoids the use of proprietary tools [25] for conducting state-space exploration analysis. -the achievement of concrete tools in Java for RT-DEVS simulation and final system implementation.…”

Temporal verification of RT-DEVS models with implementation aspects

“…All of this makes it possible to build a finite vertex time reachability graph based on the concept of time zones [Alur and Dill 1994] [Hwang and Zeigler 2009], which is the basis for exhaustive property analysis of system behaviour. The work described in this paper is concerned in particular with the use of real-time DEVS (RT-DEVS) [Song and Kim 2005] for the development of time dependent systems. RT-DEVS belongs to the FD-DEVS modelling framework, but differs from FD-DEVS in the time specification of phases and for the adoption of an explicit communication model.…”