Application specific hardware architecture for high-throughput short-length LDPC decoders

Abstract

LDPC codes have been intensively used in various wireless communication applications, due to their increased BER performance. The present paper summarizes the state of the art applications of short length LDPC codes and proposes FPGA based application specific hardware architectures for shortlength LDPC decoders. The decoding algorithms considered for implementation are both belief propagation and min-sum algorithm. Due to the increased BER performances, the proposed architecture make use of parallel computation capabilities offered by FPGA technology in order to implement the belief propagation algorithm. In spite of the iterative nature and increased computational complexity of the LDPC decoding algorithm, the proposed architecture achieves high-throughput, mandatory in real-time application and data transmission. The architecture for the LDPC belief propagation based decoder is based on arctangent hyperbolic function approximation used for check nodes update.

A high throughput configurable partially-parallel decoder architecture for Quasi-Cyclic Low-Density Parity-Check Codes

“…Very high throughputs can be achieved this way but the high costs, induced by the large area requirements and the high architectural and routing complexity, limits employability. This approach is generaly restricted to applications with very high throughputs requirements but limited code block lengths [4], [5]. The third approach is based on partial-parallel decoding [6]- [8].…”