Application Specific Instruction Set Processor for Adaptive Video Motion Estimation

Abstract

Motion estimation is the most demanding operation of a video encoder, corresponding to at least 80% of the overall computational cost. With the proliferation of portable handheld devices that support digital video coding, dataadaptive motion estimation algorithms have been required to dynamically configure the search pattern not only to avoid unnecessary computations and memory accesses but also to save energy. This paper proposes an Application Specific Instruction Set Processor (ASIP) to implement data-adaptive motion estimation algorithms, that is characterized by a specialized data-path and minimum and optimized instruction set. Due to its low-power nature, this architecture is specially adequate to develop motion estimators for portable, mobile and battery supplied devices. A cycle-based accurate simulator was also developed for the proposed ASIP and fast and data-adaptive search algorithms have been implemented, namely, the four-step search and the motion vector field adaptive search algorithms. Based on the proposed ASIP and the considered adaptive algorithms, several motion estimators were synthesized in 0 .13 μm CMOS technology. Experimental results show that very-low power adaptive motion estimators have been achieved to encode QCIF video sequences.

Integrated video motion estimator with Retinex-like pre-processing for robust motion analysis in automotive scenarios: algorithmic and real-time architecture design

“…design, supported by languages for processor architecture description such as LISAtek [27,28], and synthesis on standard-cell CMOS technologies of an ASIP. As already proved in literature [28][29][30][31][32][33][34][35][36][37][38] for hardware implementation of a specific class of digital signal processing algorithms, including video and image processing as discussed in our previous works [24,25,39], ASIPs offer a better trade-off between flexibility and performance versus classic ASICs and DSPs solutions. By exploiting the ASIPs paradigm the designer can achieve flexibility within an application domain, being able to accomplish a group of functionalities using a set of common operations.…”

High Acceleration for Video Processing Applications Using Specialized Instruction Set Based on Parallelism and Data Reuse

“…However, they incur high computational cost thus the need for specifically designed system to perform them in realtime. From the available literature, specific micro-architecture have been designed to perform BME algorithms [5], however this work is focused on extending a standard processor and presents the acceleration reached with the added instruction set. MC-FRC algorithms are based on motion estimation, which is also the most computationally demanding part of the algorithm, but video codecs also use extensively block motion estimation.…”

ASIP-based reconfigurable architectures for power-efficient and real-time image/video processing

“…However, one limitation of most ASIPs proposed in literature [1][2][3][4][5][6][7][8] is that their flexibility is only at the software level, i.e. the hardware implementation cannot be changed after the silicon fabrication [9].…”

“…ASIPs are flexible within an application domain, being able to accomplish a group of functionalities using a set of common operations. ASIP designs have been proposed in literature for motion estimation [1,4], Viterbi or LDPC channel coding/decoding [2,3], GNSS receiver [6], Discrete Cosine Transform [8], Fast Fourier Transform [7,8], and cryptography [9]. Since they are optimized towards certain applications, ASIPs combine the high performance and efficiency of a dedicated solution with the flexibility of a programmable solution.…”

“…In the most recent panorama [1][2][3][4][5][6][7][8][9][10][11][12] of digital processing systems, the design of application specific instruction-set processors (ASIPs) is gaining ground to fill the gap between ASICs and DSPs. ASIPs are flexible within an application domain, being able to accomplish a group of functionalities using a set of common operations.…”