ARA: Cross-Layer approximate computing framework based reconfigurable architecture for CNNs

Gong, Yu; Liu, Bo; Ge, Wei; Shi, Longxing

doi:10.1016/j.mejo.2019.03.011

Cited by 16 publications

(10 citation statements)

References 12 publications

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“…For DNN processing, the power consumption of multiplications is much higher than that of other operations. Therefore, in our previous work [15], we also tried to replace most multiplication operations with addition operations in the convolution layers. This approach can significantly reduce the energy consumption of multiplica-tion operations in convolution layers for image recognition applications with low accuracy requirements.…”

Section: B Approximate Computing For Dnnsmentioning

confidence: 99%

EERA-KWS: A 163 TOPS/W Always-on Keyword Spotting Accelerator in 28nm CMOS Using Binary Weight Network and Precision Self-Adaptive Approximate Computing

Liu

Wang²,

et al. 2019

IEEE Access

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This paper proposed an energy-efficient reconfigurable accelerator for keyword spotting (EERA-KWS) based on binary weight network (BWN) and fabricated in 28-nm CMOS technology. This keyword spotting system consists of two parts: the feature extraction based on melscale frequency cepstral coefficients (MFCC) and the keywords classification based on a BWN model, which is trained through the Google's Speech Commands database and deployed on our custom. To reduce the power consumption while maintaining the system recognition accuracy, we first optimize the MFCC implementation with approximate computing techniques, including Pre-emphasis coefficient transformation, rectangular Mel filtering, Framing and FFT optimization. Then, we propose a precision self-adaptive reconfigurable accelerator with digital-analog mixed approximate computing units to process the BWN efficiently. Based on the SNR prediction of background noise and post-detection of network output confidence, the BWN accelerator data path can be dynamically and adaptively reconfigured as 4, 8, or 16 bits. For the BWN accelerator, we proposed a time-delay based addition unit to process bit-wise approximate computing for the convolution layers and fully connected layers, and a LUT based unit for the activation layers. Implemented under TSMC 28 nm HPC+ process technology, the estimated power is 77.8 µW ∼ 115.9µW, the energy efficiency can achieve 163 TOPS/W, which is over 1.8× better than the state-of-the-art architecture.

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Section: B Approximate Computing For Dnnsmentioning

confidence: 99%

EERA-KWS: A 163 TOPS/W Always-on Keyword Spotting Accelerator in 28nm CMOS Using Binary Weight Network and Precision Self-Adaptive Approximate Computing

Liu

Wang²,

et al. 2019

IEEE Access

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“…Power is simulated for a convolution of a 256 ✕ 256 image with a 3 ✕ 3 filter. Results show that the proposed memorybased multiplier attains 18.4% and 29.4% reductions in the area and (c) back-to-back placement of bitcells power, respectively, compared with the state-of-the-art memory-based multiplier [4].…”

Section: Memory Arraymentioning

confidence: 99%

An area‐efficient memory‐based multiplier powering eight parallel multiplications for convolutional neural network processors

Choi

Cho

Nam

2021

Electronics Letters

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Convolutional neural network (CNN) is widely used for various deep learning applications because of its best-in-class classification performance. However, CNN needs several multiply-accumulate (MAC) operations to realize human-level cognition capabilities. In this regard, an area-efficient multiplier is essential to integrate a large number of MAC units in a CNN processor. In this letter, we present an area-efficient memory-based multiplier targeting CNN processing. The proposed architecture adopts a 32-port memory shared across eight multiplications. Simulation results show that area is reduced by 18.4% compared with the state-of-the-art memory-based multiplier.

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“…[24] proposed a uniform affine quantization to generate a quantized convolution kernel and expressed in 8-bit unsigned integer and dynamic range. [41] proposed dynamic layered application of different convolution implementation and quantization on CNN to reduce computational complexity, including the quantization of Winograd convolution. [42] proposed to apply Winograd convolution to an 8-bit network and use learning to solve the problem of accuracy loss.…”

Section: Low Precision and Quantizationmentioning

confidence: 99%

“…[87], [88] used high-efficiency Winograd convolution on IoT devices to achieve high performance. [41], [89], [90] used random calculation and approximate calculation to complete the implementation. [91] is implemented on ReRAM, which improves data reuse based on tiles, and [48] Many frameworks integrate Winograd convolution to improve model execution efficiency.…”

Section: Cpumentioning

confidence: 99%

Fast Convolution based on Winograd Minimum Filtering: Introduction and Development

Gan¹,

Huang²

2021

Computer Science and Information Technology Trends

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Convolutional Neural Network (CNN) has been widely used in various fields and played an important role. Convolution operators are the fundamental component of convolutional neural networks, and it is also the most time-consuming part of network training and inference. In recent years, researchers have proposed several fast convolution algorithms including FFT and Winograd. Among them, Winograd convolution significantly reduces the multiplication operations in convolution, and it also takes up less memory space than FFT convolution. Therefore, Winograd convolution has quickly become the first choice for fast convolution implementation within a few years. At present, there is no systematic summary of the convolution algorithm. This article aims to fill this gap and provide detailed references for follow-up researchers. This article summarizes the development of Winograd convolution from the three aspects of algorithm expansion, algorithm optimization, implementation, and application, and finally makes a simple outlook on the possible future directions.

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ARA: Cross-Layer approximate computing framework based reconfigurable architecture for CNNs

Cited by 16 publications

References 12 publications

EERA-KWS: A 163 TOPS/W Always-on Keyword Spotting Accelerator in 28nm CMOS Using Binary Weight Network and Precision Self-Adaptive Approximate Computing

EERA-KWS: A 163 TOPS/W Always-on Keyword Spotting Accelerator in 28nm CMOS Using Binary Weight Network and Precision Self-Adaptive Approximate Computing

An area‐efficient memory‐based multiplier powering eight parallel multiplications for convolutional neural network processors

Fast Convolution based on Winograd Minimum Filtering: Introduction and Development

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