Architectural enhancements in Stratix V™

Abstract

This paper describes architectural enhancements in the Altera Stratix-V™ FPGA architecture, built on a 28nm TSMC process, together with the data supporting those choices. Among the key features are time borrowing flip-flops, a doubling of the number of flip-flops per LUT compared to previous Stratix architectures, a simplified embedded 20kb dual-port RAM block, and error correction that can correct up to 8 adjacent errors. Arithmetic performance is significantly improved using a fast adder with two levels of multi-bit skip. We also describe how the routing architecture and layout is optimized for the 28nm process to take advantage of a wider range of wire thicknesses offered on the different layers, and improvements in performance and routability are obtained without dramatic changes to the repeated floorplan of the logic plus routing fabric.

Delay-Bounded Routing for Shadow Registers

“…For example, Altera provides logic clusters that support multiple clocks (whereas Xilinx only supports one per cluster) as well as fine-grained time borrowing for flip-flops [14]. Lastly, we would like to investigate how to apply negotiated congestion into our routing algorithms.…”

On Hard Adders and Carry Chains in FPGAs

“…We have chosen a depopulated crossbar as this is common in most commercial devices [2], [5]. The depopulated crossbar is composed of four, smaller, fully populated crossbars as designed by Chiasson in [13]; this depopulation results in the soft logic block inputs being divided into four groups of ten logically equivalent pins.…”

“…The next 3 circuits (bgm, boundtop and LU32PEEng) have reductions in the critical path LUT depth of more than 20% when targeting the U-CLA architecture, even though no hard adders occur on their critical paths. This indicates that adder logic was likely timing critical in the Soft architecture 2 , but has sped up enough to move off the critical path in the U-CLA architecture. Interestingly, while these 3 circuits have an average LUT depth that is 28% lower when targeting U-CLA vs. Soft, only LU32PEEng speeds up significantly, and the average delay reduction across the 3 designs is only 7%.…”

“…This argument has held sway in the case of adder-type arithmetic functions -they appear often and hardened adders are much faster than soft adders. Consequently, commercial devices commonly have hardened adder and/or carry logic and routing [2] [3] [4] [5]. Indeed, hardened arithmetic structures have been a longstanding feature of commercial FPGAs, yet there has been no comprehensive published study of the performance benefits they offer on complete designs or their cost in terms of area; this paper aims to fill that gap.…”

“…The interaction between the soft logic and the adder is flexible; the adder can either be driven by a 6-LUT and a logic block input pin or be driven by two 5-LUTs with shared inputs. The Altera Stratix V architecture uses a two-level carry-skip adder architecture [2]. Each soft logic block contains ten 2-bit carryskip adders that can be cascaded with dedicated links.…”