Architectural implications and process development of 3-D VLSI Z-axis interconnects using through silicon vias

Abstract

A through-silicon via (TSV) process provides a means of implementing complex, multichip systems entirely in silicon, with a physical packing density many times greater than today's advanced multichip modules. This technology overcomes the resistance-capacitance (RC) delays associated with long, in-plane interconnects by bringing out-of-plane logic blocks much closer electrically, and provides a connection density that makes using those blocks for random logic possible by even small system partitions. TSVs and three dimensional (3-D) stacking technology have the potential to reduce significantly the average wire length of block-to-block interconnects by stacking logic blocks vertically instead of spreading them out horizontally. Although TSVs have great potential, there are many fabrication obstacles that must be overcome. This paper discusses the architectural possibilities enabled by TSVs, and the necessary TSV dimensions for dense -axis interconnect among logic blocks. It then describes the TSV requirements for the Defense Advanced Research Projects Agency (DARPA)-funded Vertically Integrated Sensor Arrays (VISA) program, and how those requirements differ from a more general purpose TSV technology. Finally, the TSV fabrication process being implemented at the University of Arkansas (UA) is described in detail. Though this process is being developed for the VISA program, it embodies many of the characteristics of a widely applicable TSV technology.Index Terms-Copper plating, deep reactive ion etching (DRIE), reactive ion etching (RIE), through-silicon vias (TSV), Vertically Integrated Sensor Arrays (VISA), via processing, -axis interconnects.

Micro-Raman spectroscopy and analysis of near-surface stresses in silicon around through-silicon vias for three-dimensional interconnects

“…[1][2][3][4] Through-silicon vias (TSVs) are important elements for 3D integration providing direct dieto-die connections to form stacked structures. However, there are mechanical stresses due to the introduction of these elements, which may become critical for function and reliability of the chips.…”

Stress-Induced Delamination Of Through Silicon Via Structures

“…A critical structural element in the 3-D interconnects is the through-silicon via (TSV), which directly connects stacked structures die-to-die. Use of TSVs in 3-D integration can effectively improve system performance and reduce manufacturing costs [5][6][7].…”

An Outlook on Design Technologies for Future Integrated Systems

“…Thus, it makes more sense to realize different functions in different chips, and then enclose them together in a package. 3-D integration differs from SiP solutions because the various chips are stacked upon each other and interconnected mainly by through-silicon vias (TSVs) [115]. This technology provides an efficient way to realize physical routing in three dimensions, and enables the packing of complex and diverse functionalities in a minimal space and with shorter interconnections as compared to planar chips.…”