Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC

Ahmed, Akram Ben; Abdallah, Abderazek Ben; Kuroda, Kenichi

doi:10.1109/bwcca.2010.50

Cited by 25 publications

(7 citation statements)

References 16 publications

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“…Ramanujan et al [4] proposed oblivious algorithm named as Random partial minimal (RPM) for managing traffic load in worst case by routing packet randomly to any layer and then routing packet towards destination. By Ben et al [5] proposed the look ahead XYZ routing algorithm where it reduced the pipelining by combining switch allocation with calculating next node identifier in same stage but the proposed algorithm is not susceptible to overcome the problem of deadlock and live lock and thereby failure of algorithm in faulty nodes/ links. Here in our proposed work we are combining advantages of look ahead routing and adding feature of bypassing the faulty link or path.…”

Section: Literature Reviewmentioning

confidence: 99%

Enhancing Performance of Noc by Employing Fault Tolerant Routing Algorithm

Tapar¹

2016

IJRET

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In the state-of-art of high performance computing, Network on chip (NoC) is emerging as a new trend for inter-connection solutions to dense System on chip (SoC) design. The key advantages of NoC are high performance and scalability. Despite those improvements over the conventional shared-bus based systems, NoC are not shown as the ideal solution for the future SoC. Recently, with the three dimension (3D) technology, the 3D NoC has been designed to overcome the high power consumption, high cost communication and low throughput. In this project, 3x3x2 virtual channel router with mesh topology connection is to be designed and synthesized using Xilinx EDA tools. A 3D router design which can support at maximum seven requests simultaneously depending upon location of router in NoC. This 3D model is natural extension of 2D mesh NoC. The routing algorithm will be the Look Ahead-XYZ routing which is simple and free of deadlocks and enhances system performance by reducing packet delay. This will be suitable for ultra high speed application with low latency and low power consumption. Here in this project system is simulated using VHDL and implemented on FPGA kit of Virtex 5 LX110T.

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Section: Literature Reviewmentioning

confidence: 99%

Enhancing Performance of Noc by Employing Fault Tolerant Routing Algorithm

Tapar¹

2016

IJRET

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“…The system has a mesh-based topology, and control packets are forwarded along the network using a wormhole-like switching policy and then routed according to Dimension-Ordered Routing (DOR-XY) [9,[26][27][28][29][30]. The ECN adopts a stall-go mechanism and a matrix-arbiter as a scheduling technique.…”

Section: Photonic Routermentioning

confidence: 99%

An Energy-Efficient High-Throughput Mesh-Based Photonic On-Chip Interconnect for Many-Core Systems

Ahmed¹,

Abdallah²

2016

Photonics

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Future high-performance embedded and general purpose processors and systems-on-chip are expected to combine hundreds of cores integrated together to satisfy the power and performance requirements of large complex applications. As the number of cores continues to increase, the employment of low-power and high-throughput on-chip interconnect fabrics becomes imperative. In this work, we present a novel mesh-based photonic on-chip interconnect, named PHENIC-II, for future high-performance many-core systems. The novel architecture is based on an energy-efficient non-blocking photonic switch and a contention-aware routing algorithm. Simulation results show that the proposed system provides better bandwidth and energy efficiency when compared to conventional hybrid photonic NoC systems.

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“…A lot of multiple access techniques exists in the literature, such as Frequency Division Multiple Access (FDMA), Time-Division Multiple Access (TDMA), Wavelengh Division Multiple Access (WDMA). Multi-carriers modulation tech- Wave-guide On-chip antenna [1], [6] Main advantages Higher connectivity / shorter path High speed optical devices and links, low latency low latency / dynamic bandwidth allocation [4], [7] Power dissipation issue Shorter average path length Negligible power dissipation in optical data transport…”

Section: Introductionmentioning

confidence: 99%

Threshold-based routing algorithm for RF-NoC OFDMA architecture

Lahdhiri

Lorandel

Bourdel

2019

2019 14th International Symposium on Reconfigurable Communication-Centric Systems-on-Chip (ReCoSoC)

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Network-on-chip (NoC) is currently the chosen paradigm for interconnection in multicore architectures. On the other hand, the development of these architectures with thousands of cores leads to several issues regarding latency and power consumption, especially with conventional wired interconnects. Moreover, they do not support specific features like broadcast and multicast. Radio-Frequency NoC based on OFDMA seems an appropriate solution to overcome such issues, providing low latency for long communications and a significant communication bandwidth with a high spectral efficiency. It also permits a dynamic allocation of the available bandwidth among the different elements of the NoC, according to the communication needs. The routing algorithm has a significant impact on the overall performance of a RF-NoC, by diffusing the traffic in a suitable way between the wired and the wireless paths in order to improve the throughput and reduce the latency. In this paper, a threshold-based routing algorithm is proposed and evaluated for a 32×32 RF-NoC OFDMA architecture with 32 concurrent wireless channels. We demonstrate the importance to finely tune the threshold parameter to achieve a certain level of performance. Simulation results show a significant improvement in terms of latency and throughput.

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Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC

Cited by 25 publications

References 16 publications

Enhancing Performance of Noc by Employing Fault Tolerant Routing Algorithm

Enhancing Performance of Noc by Employing Fault Tolerant Routing Algorithm

An Energy-Efficient High-Throughput Mesh-Based Photonic On-Chip Interconnect for Many-Core Systems

Threshold-based routing algorithm for RF-NoC OFDMA architecture

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