Architecture and VLSI Implementation of a programmable HD Real-Time Motion Estimator

Abstract

The architecture and VLSI implementation of a programmable HD real-time motion estimator is presented. Due to the programmability, main video compression standards like MPEG-2, H.264, and VC-1 are supported. A sophisticated data flow concept in combination with a VLIW approach for controlling leads to a sustained utilization of the arithmetic resources of 95%. An area efficient architecture and design of the datapath consisting of 64 parallel processing elements reduced the required complexity to 1.2 million gates. With a first VLSI implementation in 90 nm standard cell semiconductor technology a maximum clock rate of 334 MHz was achieved. This design enables real-time motion estimation in HD format with 1920x1080 pixels at 25 Hz frame rate.

Motion Estimation Architecture Using Efficient Adder-Compressors for HDTV Video Coding

“…The architectures presented by Gaedke in [4], He in [5] and Kao in [6] are based on the FS algorithm and they were designed targeting HDTV applications. QSDS-DIC (original [1] and with PU-42 and PU-82) architecture presents significant reduction in terms of area, when compared to the results presented by Gaedke [4] and He [5], where more than 30 times less gates are used, and when compared to the architecture presented by Kao [6], where more than 10 times less gates are used. However, the QSDS-DIC architecture presents slightly more gates than the architecture presented by Li in [12].…”

“…The developed architecture for the QSDS-DIC algorithm was compared with other published designs for ME. Table VI shows the comparisons of the original QSDS-DIC architecture, the architecture with PU-42 and PU-82 versions, and the designs presented by Li in [12], Gaedke in [4], He in [5] and Kao in [6].…”

“…The FS algorithm was chosen by Mohammadzadeh [3], Gaedke [4], He [5] and Kao [6] to develop their ME architectures. However, only Mohammadzadeh [3] synthesizes his architecture to FPGA.…”

Architectural design for the new QSDS with dynamic iteration control motion estimation algorithm targeting HDTV

“…Due to the efficiency of the QSDS-DIC algorithm, the designed architecture uses less hardware resources than other solutions, reaching the highest throughput among then. Table V shows the comparisons with the designs presented in [4], [5], [6] and [7]. The architectures presented in [6] and [7] use FS algorithm and they were designed targeting HDTV applications.…”

“…These architectures use lots of gates to achieve real time. QSDS-DIC architecture uses 42 times less gates than [6] and 35 times less gates than [7]. The architecture presented in [4] uses FS+PS4:1 and early termination algorithm and architecture [5] uses PVMFAST algorithm for a search range of 32x32 samples.…”