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The architecture and VLSI implementation of a programmable HD real-time motion estimator is presented. Due to the programmability, main video compression standards like MPEG-2, H.264, and VC-1 are supported. A sophisticated data flow concept in combination with a VLIW approach for controlling leads to a sustained utilization of the arithmetic resources of 95%. An area efficient architecture and design of the datapath consisting of 64 parallel processing elements reduced the required complexity to 1.2 million gates. With a first VLSI implementation in 90 nm standard cell semiconductor technology a maximum clock rate of 334 MHz was achieved. This design enables real-time motion estimation in HD format with 1920x1080 pixels at 25 Hz frame rate.

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For a monolithic video signal processor a special RISC processor core has been developed. In order to achieve an efficient implementation of hybrid video coding algorithms the applied harvard architecture with 16 bit data path is adapted to tasks like quantization, variable length coding and run length coding. The RISC processor's die size is 68,79 mm2 fabricated in a 0.8 pn CMOS technology. 4 Byte of program R A M and 512 Bytes of Data Memory are implemented on chip. The operating frequency is 66 MHz. AddressData Out Control

This paper discusses a VLSI based multiprocessor architecture for real-time processing of video coding applications. The architecture consists of multiple identical processing elements and is characterized as MIMD (Multiple Instruction Multiple Data). The architecture of a processing element is based on astandardprocessor core, e.g. a RISCprocessor, and a low level coprocessor. The low level coprocessor is adapted to parallel processing of convolution-like operations. The performance of the architecture is discussedwithrespectto the processing time for hybrid coding algorithms as well as to the required silicon area.