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For a monolithic video signal processor a special RISC processor core has been developed. In order to achieve an efficient implementation of hybrid video coding algorithms the applied harvard architecture with 16 bit data path is adapted to tasks like quantization, variable length coding and run length coding. The RISC processor's die size is 68,79 mm2 fabricated in a 0.8 pn CMOS technology. 4 Byte of program R A M and 512 Bytes of Data Memory are implemented on chip. The operating frequency is 66 MHz. AddressData Out Control

The video signal processor AxPe1280V has been developed for implementation of different video coding applications according to standards like ITU-T H.261/H.263, and ISO MPEG-1/2. It consists of a RISC processor supplemented by a coprocessor for convolution-like low-level tasks. RISC and coprocessor have been implemented in a standard cell design combined with full-custom modules. The processor was fabricated in a 0.5 m CMOS technology and has a die size of 82 mm 2 . It provides a peak performance of more than 1 giga arithmetic operations per second (GOPS) at 66 MHz. For processing of very computation-intensive algorithms or high data rates, several processors can be bus-connected to form a MIMD multiprocessor system.

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The architecture and implementation of a programmable video signal processor dedicated as building block of a MIMD-based bus-connected multiprocessor system is presented. This system can either be constructed from several single processor chips, or it can be integrated on a large area integrated circuit containing several processors. The processor allows an e cient implementation of di erent video coding standards like H.261, H.263, MPEG-1 and MPEG-2. It consists of a RISC processor supplemented by a coprocessor for computation intensive convolution-like tasks, which provides a peak performance of more than 1 giga arithmetic operations per second GOPS. A large area integrated circuit integrating 9 processor elements PEs on an area of 16.6 cm 2 has been designed. Due to yield considerations redundancy concepts have been implemented, that even in the presence of production defects result in working chips utilizing a lower number of PEs. Each PE has built-in self-test BIST capabilities, which allow for an independent test of itself under the control of its integrated fault-tolerant BIST controller. Defective PEs are switched o. Only the PEs passing the BIST are used for video processing tasks. Prototypes have been fabricated in a 0.8 m CMOS process structured by masks using wafer stepping with overlapping exposures. Employing redundancy, u p t o 6 PEs per chip were functional at 66 MHz, thus providing a peak arithmetic performance of up to 6 GOPS. Keywords| BIST, hybrid video coding, large area integration, laser recon guration, MPEG, multiprocessor system, redundancy for yield enhancement, video signal processor.