Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse

Kim, Jin-Woo; Murali, Gauthaman; Park, Heechun; Qin, Eric; Kwon, Hyoukjun; Chekuri, Venkata Chaitanya Krishna; Rahman, Nael Mizanur; Dasari, Nihar; Singh, Arvind; Lee, Min-Ah; Torun, Hakki Mert; Roy, Kallol; Swaminathan, Madhavan; Mukhopadhyay, Saibal; Krishna, Tushar; Lim, Sung Kyu

doi:10.1109/tvlsi.2020.3015494

Cited by 63 publications

(9 citation statements)

References 19 publications

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“…However, in the chiplet-based architecture, the max wirelength can be much longer than that of SoC. For example, in the chiplet-based architecture containing 64 cores [24], the max wirelength can reach about 10 mm.…”

Section: Simchiplet: Chiplet Simulation Methodsmentioning

confidence: 99%

“…Therefore, according to the HPWL between the chiplets on the silicon interposer and the relationship between the latency and wirelength [24], we map the wirelength into six ranges in Moreover, the power consumption on wires is highly related to the wirelength, and according to [24], the power consumption increases linearly by 0.037 pJ/bit×mm. Therefore, moving the chiplet-pair with a higher communication frequency closer will decrease the power consumption and improve the overall performance.…”

Section: Simchiplet: Chiplet Simulation Methodsmentioning

confidence: 99%

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Scene-aware Learning Network for Radar Object Detection

Zheng

Yue

Keutzer

et al. 2021

Proceedings of the 2021 International Conference on Multimedia Retrieval

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Object detection is essential to safe autonomous or assisted driving. Previous works usually utilize RGB images or LiDAR point clouds to identify and localize multiple objects in self-driving. However, cameras tend to fail in bad driving conditions, e.g. bad weather or weak lighting, while LiDAR scanners are too expensive to get widely deployed in commercial applications. Radar has been drawing more and more attention due to its robustness and low cost. In this paper, we propose a scene-aware radar learning framework for accurate and robust object detection. First, the learning framework contains branches conditioning on the scene category of the radar sequence; with each branch optimized for a specific type of scene. Second, three different 3D autoencoder-based architectures are proposed for radar object detection and ensemble learning is performed over the different architectures to further boost the final performance. Third, we propose novel scene-aware sequence mix augmentation (SceneMix) and scene-specific post-processing to generate more robust detection results. In the ROD2021 Challenge, we achieved a final result of average precision of 75.0% and an average recall of 81.0%. Moreover, in the parking lot scene, our framework ranks first with an average precision of 97.8% and an average recall of 98.6%, which demonstrates the effectiveness of our framework. CCS CONCEPTS• Computing methodologies → Object detection; Scene understanding; Neural networks.

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Section: Simchiplet: Chiplet Simulation Methodsmentioning

confidence: 99%

Section: Simchiplet: Chiplet Simulation Methodsmentioning

confidence: 99%

Scene-aware Learning Network for Radar Object Detection

Zheng

Yue

Keutzer

et al. 2021

Proceedings of the 2021 International Conference on Multimedia Retrieval

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“…Note that in chiplet-based integration, it is highly common for each chiplet to have dedicated regulators [ 96 ]. These regulators are typically placed within the interposer to save area and realize passive devices with high quality factors [ 97 ], as shown in Figure 8 . This technique, however, introduces an important security vulnerability by providing a more direct approach for power covert channels.…”

Section: Covert Channel Attacks In 25d/3d Icsmentioning

confidence: 99%

Covert Channel Communication as an Emerging Security Threat in 2.5D/3D Integrated Systems

Miketic

Dhananjay

Salman

2023

Sensors

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In this paper, first, a broad overview of existing covert channel communication-based security attacks is provided. Such covert channels establish a communication link between two entities that are not authorized to share data. The secret data is encoded into different forms of signals, such as delay, temperature, or hard drive location. These signals and information are then decoded by the receiver to retrieve the secret data, thereby mitigating some of the existing security measures. The important steps of covert channel attacks are described, such as data encoding, communication protocol, data decoding, and models to estimate communication bandwidth and bit error rate. Countermeasures against covert channels and existing covert channel detection techniques are also summarized. In the second part of the paper, the implications of such attacks for emerging packaging technologies, such as 2.5D/3D integration are discussed. Several covert channel threat models for 2.5D/3D ICs are also proposed.

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“…The substance of a 2.5 D integration is called silicon interposer, which consists of the top to bottom through silicon via (TSV) and the routings on redistribution layer (RDL), as the wafer-level processing is significantly accurate compared with the traditional printed circuit board (PCB) process, detector arrays with ignorable dead space and extremely short front-back signal readout can be implemented. However, the state-of-the-art silicon interposer is normally below 100 µ m thick, while the size can only reach up to 50 × 50 mm (Coudrain et al , 2019; Lee et al , 2016; Kim et al , 2020), which leads to a few issues that, for one, the current thickness is not able to sustain its own mechanical strength with the detector/readout array often sits as standalone in large science facilities instead of on a rigid PCB in consumer electronics, as for another, the target interposer size should be as large as possible to reduce the expanses on the installation of the components. Therefore, a moderation of the current interposer toward large-sized, standalone properties is needed.…”

Section: Introductionmentioning

confidence: 99%

Double-sided silicon vias (DSSVs) interconnection for large-sized interposer fabrication

Yang

Dai

Cao

et al. 2023

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Purpose A large-scale detection system with more data in short time bins, small dead space and small signal identification is the ideology the scientists pursuing. These proposed demands are able to be solved by 2.5 D integration. The substance of a 2.5 D integration is called silicon interposer, which consists of the through silicon via (TSV) and redistribution layer. However, the state-of-the-art silicon interposer is not able to sustain its own mechanical strength with the detector/readout array often sitting as standalone in large science facilities and fails to reduce the expansions on the installation of the components due to its insufficient thickness and size. This study aims to propose a moderation of current interposer with large-sized, standalone properties. Design/methodology/approach This paper proposes an interposer based on double-sided silicon vias (DSSVs) interconnection. Unlike conventional interposer that is interconnected by TSVs, DSSVs interposer is interconnected by top vias (T-vias) and bottom vias (B-vias). Findings The fabrication process of DSSVs interposer is introduced, and the superiority of the double-sided interconnection process with two etch-stop layers is described in detail. The impact of different T-vias depth on DSSVs interconnections in the same wafer is discussed and two times PI opening processes are proposed to eliminate air bubbles in the B-via. The relationship between the interposer thickness and warpage is studied by finite element analysis simulation and experiment. The prototype of the DSSVs interposer with a size of 100 × 100 mm and a thickness of 318.2 µm is fabricated, and electrical tests including short tests and continuity tests are carried out. Originality/value This paper proposes a large-sized and stand-alone interposer based on DSSVs interconnection.

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Architecture, Chip, and Package Codesign Flow for Interposer-Based 2.5-D Chiplet Integration Enabling Heterogeneous IP Reuse

Cited by 63 publications

References 19 publications

Scene-aware Learning Network for Radar Object Detection

Scene-aware Learning Network for Radar Object Detection

Covert Channel Communication as an Emerging Security Threat in 2.5D/3D Integrated Systems

Double-sided silicon vias (DSSVs) interconnection for large-sized interposer fabrication

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