Architecture of a VLSI instruction cache for a RISC

Abstract

A cache was first used in a commercial computer in 1968, 1 and researchers have spent the last 15 years analyzing caches and suggesting improvements. In designing a VLSI instruction cache for a RISC microprocessor we have uncovered four ideas potentially applicable to other VLSI machines. These ideas provide expansible cache memory, increased cache speed, reduced program code size, and decreased manufacturing costs. These improvements blur the habitual distinction between an instruction cache and an instruction fetch unit. The next four sections present the four architectural ideas, followed by a section on performance evaluation of each idea. We then describe the implementation of the cache and finally summarize the results.

INTERPLAY: An Intelligent Model for Predicting Performance Degradation due to Multi-cache Way-disabling

“…Cache-disabling can be applied at different granularities, by disabling the line or the entire cache-way that contains a fault [7]- [10], [12]. Figure 1 shows a performance analysis of cache way-disabling for a processor with a two-level cache hierarchy, for 21 different applications and all possible cache-Fig.…”

A cache-defect-aware code placement algorithm for improving the performance of processors

“…A more sophisticated way is disabling only the defective cache-line because the existence of a defect in a cache-line does not affect other cache lines. This can be done by using an extra bit added to the flag bits associated with each block and using the added bit for marking a faulty cache block [10]. If the bit is one, the corresponding cache block will not be used for replacement in case of a cache miss.…”

“…Other names used in literature are: availability bit [3], the second valid bit [4] and purge bit [5]. The idea of adding the FT-bit was initially proposed in [10].…”