Area- and Power-Efficient Architecture for High-Throughput Implementation of Lifting 2-D DWT

Abstract

We have suggested a new data-access scheme for the computation of lifting two-dimensional (2-D) discrete wavelet transform (DWT) without using data transposition. We have derived a linear systolic array directly from the dependence graph (DG) and a 2-D systolic array from a suitably segmented DG for parallel and pipeline implementation of 1-D DWT. These two systolic arrays are used as building blocks to derive the proposed transposition-free structure for lifting 2-D DWT. The proposed structure requires only a small on-chip memory of (4N + 8P ) words and processes a block of P samples in every cycle, where N is the image width. Moreover, it has small output latency of nine cycles and does not require control signals which are commonly used in most of the existing DWT structures. Compared with the best of the existing high-throughput structures, the proposed structure requires the same arithmetic resources but involves 1.5N less on-chip memory and offers the same throughput rate. ASIC synthesis result shows that the proposed structure for block size 8 and image size 512 × 512 involves 28% less area, 35% less area-delay product, and 27% less energy per image than the best of the corresponding existing structures. Apart from that, the proposed structure is regular and modular; and it can be easily configured for different block sizes.Index Terms-Block processing, discrete wavelet transform (DWT), lifting, systolic VLSI, 2-D DWT.

Efficient Design for Radix-8 Booth Multiplier and Its Application in Lifting 2-D DWT

“…Due to less ADP, we have chosen the proposed radix-8 generic-constant fixed-width multiplier design over the existing radix-4 generic-constant Booth multiplier design to develop area-delayefficient fixed-point architectures for computation of 2-D DWT. We have considered the existing multiplier-based 2-D DWT structure of [13] and modified this structure to take advantage of radix-8 generic-constant multiplier.…”

“…Since, no redundant computation is available in lifting 2-D DWT, there is no scope to reduce multiplier complexity without compromising on the throughput rate. However, we observe that many multipliers of block-lifting 2-D DWT structures [12,13,15,17] share a common input operand. A group of multipliers with a common multiplying operand can select their partial product terms from a common set using Booth encoding scheme.…”

“…Interestingly, the lifting-based 2-D DWT structure involves constant multiplication. The lifting 2-D DWT structure of block size P involves 4.5P multipliers [13]. One operand of these 4.5P multipliers is one of the four lifting constants {α, β, γ , δ} or two scaling constants {k 2 , 1/k 2 }.…”

A Block based Area-Delay Efficient Architecture for Multi-Level Lifting 2-D DWT

“…Unlike RPA-based designs, folded design involves simple control circuitry and it has 100 % HUE. Keeping this in view, several architectures based have been proposed for efficient implementation of lifting 2-D DWT [5][6][7][8][9][10][11][12]. Most of the designs differ by their number of arithmetic components, on-chip memory, cycle period and throughput rate.…”

“…Low-pass block a (9,8) a (10,8) a (11,8) a (12,8) a (13,8) a (14,8) a (15,8) h (4,4) h (4,5) h (4,7) h (4,8) l (4,5) l (4,6) l (4,7) l (4,8) …”