Area and Power Modeling for Networks-on-Chip with Layout Awareness

Abstract

Networks-on-Chip (NoCs) are emerging as scalable interconnection architectures, designed to support the increasing amount of cores that are integrated onto a silicon die. Compared to traditional interconnects, however, NoCs still lack well established CAD deployment tools to tackle the large amount of available degrees of freedom, starting from the choice of a network topology. “Silicon-aware” optimization tools are now emerging in literature; they select an NoC topology taking into account the tradeoff between performance and hardware cost, that is, area and power consumption. A key requirement for the effectiveness of these tools, however, is the availability of accurate analytical models for power and area. Such models are unfortunately not as available and well understood as those for traditional communication fabrics. Further, simplistic models may turn out to be totally inaccurate when applied to wire dominated architectures; this observation demands at least for a model validation step against placed and routed devices. In this work, given an NoC reference architecture, we present a flow to devise analytical models of area occupation and power consumption of NoC switches, and propose strategies for coefficient characterization which have different tradeoffs in terms of accuracy and of modeling activity effort. The models are parameterized on several architectural, synthesis-related, and traffic variables, resulting in maximum flexibility. We finally assess the accuracy of the models, checking whether they can also be applied to placed and routed NoC blocks.

A New Approach to Model the Effect of Topology on Testing Using Boundary Scan

“…Thus it is not suitable to explore trade-offs in the design. Later in [13], two models for power and area analysis of NoCs were proposed. They used a RTL level approach for modelling as well.…”

DSE and profiling of multi-context coarse-grained reconfigurable systems

“…Accurate analytical models would result extremely useful to allow computing the evaluation functions of all the design points according to the given possible parameters. Such models, for example, have been derived in [15] to introduce technology-awareness in the early stage characterization of a highly parametric Network-on-Chip architecture. In our case such methodologies may be coupled with the graph-based estimations presented in Sect.…”

Exploiting FPGAs for technology-aware system-level evaluation of multi-core architectures

“…The paper also quantifies in three orders of magnitude the gain in emulation speed that can be achieved with the use of FPGA prototyping, comparing it with one of the previously cited software-based simulators. The framework proposed in our work extends these approaches, coupling the extraction of a number of metrics with the use of analytical models ( [11]) related to a prospective ASIC implementation of the considered system, enabling the estimation of physical characteristics, such as power and area consumption. Moreover, we point out in detail the effort related to the implementation of the architecture under prototyping on FPGA and we introduce some synthesis techniques aimed to reduce it.…”

“…The metrics extracted with the FPGAbased emulation of the system are then passed as input to the analytic models for the estimation of the physical figures of interest. An example of such kind of models is included in the framework and presented in [11], referring to the power consumption and area occupation of the ×pipes NoC building blocks. The accuracy of these models described in [11] is assessed in the paper to be lower then 10% when complete topologies are considered, with respect to post layout analysis of real ASIC implementations.…”