Area and Power Modeling Methodologies for Networks-on-Chip

Meloni, Paolo; Carta, Salvatore; Argiolas, Raffaele; Raffo, Luigi; Angiolini, Federico

doi:10.1109/nanonet.2006.346216

Cited by 12 publications

(4 citation statements)

References 24 publications

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“…In [79] and in [80] Networks are configurable by a set of nineteen parameters that represent the network configuration and can be divided in two main categories: network architecture and router architecture. The traffic description involves three additional parameters.…”

Section: Application Examplesmentioning

confidence: 99%

Multi-Core Embedded Systems

2010

Embedded Multi-Core Systems

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In recent years, due to the continuous development in the field of silicon technology, it is possible to implement complex electronic systems in a single integrated circuit. Systemson-Chip (SoC) have favored the explosion of the market of electronic appliances: small mobile devices, which provide communications and information capabilities for consumer electronics and industrial automation. These devices require complex electronic and high levels of system integration and need to be delivered in a very short time in order to meet their market window.The design complexity of these systems requires new design methodologies and the development of a seamless design flow that integrates existing and emerging tools. The International Technology Roadmap for Semiconductors (ITRS) [1] and MEDEA+ roadmap [2] evidence some key points that Electronic Design Automation Companies must consider in order to deal with such design complexity, among them: 1 2 CHAPTER 1. POWER OPTIMIZATION AND RELIABILITY ISSUES • Intellectual Property Reuse Intellectual Property (IP) reuse is becoming critical for an efficient system development; the need to shorten the time to market is stimulating re-usability of both hardware and software. A good way to keep design costs under control is to minimize the amount of new designs that are required each time a new SoC is developed: reuse existing design components where possible. The development of reusable IPs requires:the development of standards, including general constraints and guidelines, as well as executable specifications for intra-and inter-company IP exchange, such as Sys-temC, XML and UML [3],the creation of parameterizable, qualified and validated IPs, the use of hierarchical reuse methodology, allowing the reuse of the IPs and of the testbenches at different levels of abstraction.Furthermore, the IP reuse methodology is indispensable when the design of a system is developed in cooperation between different companies, or when the design center is distributed all over the world and consequently the project management is distributed. A lot of work have been done in the development of standards for IP qualification. The SPIRIT Consortium [4] developed the IP-XACT specification to enable rapid, reliable deployment of IPs into advanced design environments. The Virtual Socket Interface Alliance (VSIA) [5] developed the international standard QIP (Quality Intellectual Property) for measuring IP quality. OpenCores [6] is the world's largest community for development of open source hardware IPs. • Low Power DesignThe continuous progress of micro and nano technologies led to a growing integration and clock frequency increment in electronics systems. These combined effects lead to an increment both in power density and energy dissipation, with important consequences above all in portable systems. Some design and technology issues related to power efficiency are becoming crucial, in particular for power optimized cell-libraries, clockgating and clock-trees optimization, and dynamic power management. ...

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Section: Application Examplesmentioning

confidence: 99%

Multi-Core Embedded Systems

2010

Embedded Multi-Core Systems

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“…We have built accurate analytical models for calculating the power consumption, area and delay of the Â pipes network components [48]. To get an accurate estimate of these parameters, they are extracted from real placed&routed NoC designs.…”

Section: Area Power Models For Noc Componentsmentioning

confidence: 99%

“…From this plot we can infer that at low operating frequencies, a topology with few, but large switches results in the most power optimal design. This is due to the fact that the increase in power consumption is mostly linear with the increase in switch size [48]. Thus, in a design with fewer switches, the traffic flows traverse shorter paths, thereby leading to designs with better power consumption.…”

Section: Impact Of Frequency Constraintsmentioning

confidence: 99%

Network-on-Chip design and synthesis outlook

et al. 2008

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With the growing complexity in consumer embedded products, new tendencies forecast heterogeneous Multi-Processor SystemsOn-Chip (MPSoCs) consisting of complex integrated components communicating with each other at very high-speed rates. Intercommunication requirements of MPSoCs made of hundreds of cores will not be feasible using a single shared bus or a hierarchy of buses due to their poor scalability with system size, their shared bandwidth between all the attached cores and the energy efficiency requirements of final products.To overcome these problems of scalability and complexity, Networks-On-Chip (NoCs) have been proposed as a promising replacement to eliminate many of the overheads of buses and MPSoCs connected by means of general-purpose communication architectures. However, the development of application-specific NoCs for MPSoCs is a complex engineering process that involves the definition of suitable protocols and topologies of switches, and which demands adequate design flows to minimize design time and effort. In fact, the development of suitable high-level design and synthesis tools for NoC-based interconnects is a key element to benefit from NoC-based interconnect design in nanometer-scale CMOS technologies.In this article we overview the benefits of state-of-the-art NoCs using a complete NoC synthesis flow, and a detailed scalability analysis of different NoC implementations for the latest nanometer-scale technology nodes. We present NoC-based solutions for the on-chip interconnects of MPSoCs that illustrate the benefits of competitive application-specific NoCs with respect to more regular NoC topologies regarding performance, area and power. Moreover, we show that it is currently feasible to synthesize in an automatic way a complete custom NoC interconnect from a high-level specification in few hours. Finally, we summarize future research challenges in the area of NoC interconnect design automation. r

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“…The characterization is dependent on the target technology library, but can be easily scripted and automated. A major novel feature of our study, improving on our previous work [1], is that we explore the accuracy of our modeling style against placed and routed test instances; we feel that this is an essential step given the uncertainties intrinsic in today's technology processes. We also show that model coefficients can be made even more accurate by using a placed and routed training set for characterization, albeit at a modeling effort cost, and that the remaining inaccuracies can mostly be attributed to the intrinsic variations induced by synthesis tools.…”

Section: Introductionmentioning

confidence: 99%

Area and Power Modeling for Networks-on-Chip with Layout Awareness

et al. 2007

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Networks-on-Chip (NoCs) are emerging as scalable interconnection architectures, designed to support the increasing amount of cores that are integrated onto a silicon die. Compared to traditional interconnects, however, NoCs still lack well established CAD deployment tools to tackle the large amount of available degrees of freedom, starting from the choice of a network topology. “Silicon-aware” optimization tools are now emerging in literature; they select an NoC topology taking into account the tradeoff between performance and hardware cost, that is, area and power consumption. A key requirement for the effectiveness of these tools, however, is the availability of accurate analytical models for power and area. Such models are unfortunately not as available and well understood as those for traditional communication fabrics. Further, simplistic models may turn out to be totally inaccurate when applied to wire dominated architectures; this observation demands at least for a model validation step against placed and routed devices. In this work, given an NoC reference architecture, we present a flow to devise analytical models of area occupation and power consumption of NoC switches, and propose strategies for coefficient characterization which have different tradeoffs in terms of accuracy and of modeling activity effort. The models are parameterized on several architectural, synthesis-related, and traffic variables, resulting in maximum flexibility. We finally assess the accuracy of the models, checking whether they can also be applied to placed and routed NoC blocks.

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Area and Power Modeling Methodologies for Networks-on-Chip

Cited by 12 publications

References 24 publications

Multi-Core Embedded Systems

Multi-Core Embedded Systems

Network-on-Chip design and synthesis outlook

Area and Power Modeling for Networks-on-Chip with Layout Awareness

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