Area and Throughput Analysis of Different AES Architectures for FPGA Implementations

Yadav, Disha; Rajawat, Arvind

doi:10.1109/inis.2016.026

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Area and Throughput Analysis of Different AES Architectures for FPGA Implementations

Cited by 6 publications

References 6 publications

A Survey on Performance Analysis of Different Architectures of AES Algorithm on FPGA

A Survey on Performance Analysis of Different Architectures of AES Algorithm on FPGA

An AES Implementation with Improved PDL Based PUF Key Generator for IoT Devices

The 128-bit AES design by using FPGA

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