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This paper analyses a 3-phase interleaved DC-DC boost converter for the conversion of low input voltage with high input current to higher DC output voltage. The operation of the 3-phase interleaved DC-DC boost converter with multi-parallel of boost converters is controlled by interleaved of switching signals with 120 degrees phase-shifted. Therefore, with this circuit configuraion, high input current is evenly shared among the parallel units and consequently the current stress is reduced on the circuit and semiconductor devices and contributes reduction of overall losses. The simulation and hardware results show that the current stress and the semiconductor conduction losses were reduced approximately 33% and 32%, respectively in the 3-phase interleaved DC-DC boost converter compared to the conventional DC-DC boost converters. Furthermore, the use of interleaving technique with continuous conduction mode on DC-DC boost converters is reducing input current and output voltage ripples to increase reliability and efficiency of boost converters.

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Advanced Encryption Standard (AES) is a common symmetric encryption algorithm and widely implemented in Wireless Local Area Network (WLAN) and Bluetooth controller for security services in its application. This paper presents a 128-bit data path with 128-bit, 192-bit or 256-bit key size. The purpose of the design is high throughput and low area design of AES. The AES methodology is by using Field-Programmable Gate Array (FPGA) and Xilinx Virtex-7 XC7VX485T as a tool to obtain simulation results through Verilog Hardware Description Language (HDL). This design utilized a 2730 Slices with the throughput of 12.9 Gbps. The design is suitable for the portable device application which requires data security with a high throughput and speed.

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