The purpose of this study is to analyze the operation and design of symmetrical and asymmetrical multilevel inverter structures with reduced number of switching devices. In this study, the term of conventional inverter is defined as a single cascaded inverter. Specifically, the inverter operates in three complete loops and only produces 2-level and 3-level of output voltages. Usually, cascaded structure suffers from the high total harmonic distortion. Thus, by considering multilevel structure of inverter, low total harmonic distortion reduction and voltage stress reduction on switching devices can be archived. Sinusoidal pulse width modulation and modified square pulse width modulation are used as modulation techniques in switching schemes of the designed multilevel inverters. The findings indicate that, the designed multilevel structure cause low total harmonics distortion at the output voltage. Furthermore, the asymmetrical structure is producing the same output voltage levels with reduced number of switching devices compared to the symmetrical structure is experimentally confirmed. The findings show that the total harmonic distortion for 7-level (symmetrical) and 9-level (asymmetrical) are 16.45% and 15.22%, respectively.

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This paper analyses a 3-phase interleaved DC-DC boost converter for the conversion of low input voltage with high input current to higher DC output voltage. The operation of the 3-phase interleaved DC-DC boost converter with multi-parallel of boost converters is controlled by interleaved of switching signals with 120 degrees phase-shifted. Therefore, with this circuit configuraion, high input current is evenly shared among the parallel units and consequently the current stress is reduced on the circuit and semiconductor devices and contributes reduction of overall losses. The simulation and hardware results show that the current stress and the semiconductor conduction losses were reduced approximately 33% and 32%, respectively in the 3-phase interleaved DC-DC boost converter compared to the conventional DC-DC boost converters. Furthermore, the use of interleaving technique with continuous conduction mode on DC-DC boost converters is reducing input current and output voltage ripples to increase reliability and efficiency of boost converters.

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This paper discusses the current total harmonic distortion (THDi) and voltage ripple minimization of SEPIC converter based on parameters design optimization. This conventional PFC SEPIC converter is designed to operate in discontinuous conduction mode in order to achieve almost unity power factor. The passive components, i.e., inductor and capacitor are designed based on switching frequency and resonant frequency. Meanwhile, the ranges of duty cycle for buck and boost operations are between 0