Optimization of PFC SEPIC Converter Parameters Design for Minimization of THD and Voltage Ripple

Abstract

This paper discusses the current total harmonic distortion (THDi) and voltage ripple minimization of SEPIC converter based on parameters design optimization. This conventional PFC SEPIC converter is designed to operate in discontinuous conduction mode in order to achieve almost unity power factor. The passive components, i.e., inductor and capacitor are designed based on switching frequency and resonant frequency. Meanwhile, the ranges of duty cycle for buck and boost operations are between 0<D<0.5 and 0.5<D<1, respectively, for the output voltage variation of the converter. The principle of the parameters design optimization is based on the balancing energy compensation between the input capacitor and output inductor. The experimental results show that, the current THD is reduced to 2.66% from 70.9% after optimization process is conducted. Furthermore, it is confirmed that the output voltage ripple frequency is always double from the input line frequency, fL = 2fout and the output voltage ripple is always lower than the maximum input voltage ripple. Therefore, the designed parameters of the experimental converter is confirmed with approximately 65 W of the converter output power.

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