Area efficient DSP datapath synthesis

Duncan, Andrew A.; Hendry, D.

doi:10.1109/eurdac.1995.527398

Cited by 6 publications

(5 citation statements)

References 18 publications

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“…Both of these research works claimed an impressive area reduction and are targeted toward data-intensive DSP Systems. Similarly, Duncan et al proposed COBRA, a behavioral HLS tool for data-oriented applications [10]. They performed datapath optimizations by using simulated annealing algorithms and the key contribution was to use actual physical target architectures while generating the final datapath.…”

Section: A Hls Design-flowsmentioning

confidence: 99%

A design-flow for high-level synthesis and resource estimation of reconfigurable architectures

Pasha

Siddiqui

Farooq

2015

2015 10th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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Field Programmable Gate Arrays (FP-GAs), due to their programmability, have become a popular design choice for control and processing blocks of an embedded system. However, this flexibility makes them larger, slower and less power-efficient than Application Specific Integrated Circuits (ASICs) and hinders their use in low-area and low-power applications. On the other hand, ASICs have their inherent drawbacks like lack of programmability and inflexibility. The solution is reconfigurable architectures that have improved flexibility over ASICs and better resource utilization than FPGAs. However, designing a reconfigurable architecture is a daunting task in itself due to lack of high-level design-flow support. This paper proposes an automated design-flow for system-level synthesis and resource estimation for generic as well as custom reconfigurable architectures. The experimental results show that the generated reconfigurable architectures are 79% more area and 76% more power efficient than generic academic FPGA-based implementations.

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Section: A Hls Design-flowsmentioning

confidence: 99%

A design-flow for high-level synthesis and resource estimation of reconfigurable architectures

Pasha

Siddiqui

Farooq

2015

2015 10th International Conference on Design &Amp; Technology of Integrated Systems in Nanoscale Era (DTIS)

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“…After implementation of the RTL code, timing verification needs to be done for proper operation. RTL design abstracts logic structures, timing and registers [2]. Because of this, every clock change causes a state change in the design.…”

Section: Introductionmentioning

confidence: 99%

Matrix Operations Design Tool for FPGA and VLSI Systems

Aslan¹,

Saniie²

2016

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Embedded systems used in real-time applications require low power, less area and high computation speed. For digital signal processing, image processing and communication applications, data are often received at a continuously high rate. The type of necessary arithmetic functions and matrix operations may vary greatly among different applications. The RTL-based design and verification of one or more of these functions could be time-consuming. Some High Level Synthesis tools reduce this design and verification time but may not be optimal or suitable for low power applications. The design tool proposed in this paper can improve the design time and reduce the verification process. The design tool offers a fast design and verification platform for important matrix operations. These operations range from simple addition to more complex matrix operations such as LU and QR factorizations. The proposed platform can improve design time by reducing verification cycle. This tool generates Verilog code and its testbench that can be realized in FPGA and VLSI systems. The designed system uses MATLAB-based verification and reporting.

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“…Given the strong interdependence of the synthesis subtasks, COBRA-ABS formulates and solves all subproblems (in this case, module selection and allocation, operator scheduling and binding, partitioning, memory and communication scheduling and binding, and register allocation) in one optimization using a simulated annealing-based model developed from that proposed in [8]. Other approaches to integration of synthesis subtasks in the general high-level synthesis literature have included the integer programming models presented in [9] and [10] and that presented in [11].…”

Section: Introductionmentioning

confidence: 99%