AREA optimized low power arithmetic and logic unit

Rani, T. Esther; Rani, M. Asha; Rao, Rameshwar

doi:10.1109/icectech.2011.5941742

Cited by 27 publications

(10 citation statements)

References 9 publications

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“…Table 4 summarizes the performance comparison of M3DIC-JLFETs and M3DIC-MOSFETs. M3DICs such as the INV, NAND, NOR, 2 × 1 multiplexer (MUX) [ 29 ], D flip-flop (D-FF) [ 30 ], and 6T SRAM [ 31 ] were simulated. Their performances were compared in terms of their average static power, average dynamic power, and average delay.…”

Section: Circuit Simulation and Discussionmentioning

confidence: 99%

Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs

Ahn

2020

Micromachines

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The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed of JLFETs (M3DIC-JLFET). We validated the model by extracting the model parameters and comparing the simulation results of the technology computer-aided design and the Synopsys HSPICE circuit simulator. The performance of the M3DIC-JLFET was compared with that of the M3DIC composed of MOSFETs (M3DIC-MOSFET). The performance of a fan-out-3 ring oscillator with M3DIC-JLFET varied by less than 3% compared to that with M3DIC-MOSFET. The performances of ring oscillators of M3DIC-JLFET and M3DIC-MOSFET were almost the same. We simulated the performances of M3DICs such as an inverter, a NAND, a NOR, a 2 × 1 multiplexer, and a D flip-flop. The overall performance of the M3DIC-MOSFET was slightly better than that of the M3DIC-JLFET.

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Section: Circuit Simulation and Discussionmentioning

confidence: 99%

Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs

Ahn

2020

Micromachines

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“…Power diminishing could be achieved at Module Level or at circuit level or at architecture level [2]. In simple switch procedure select info rationale as control rationale and permits additional info signal from gate terminal [3].…”

Section: Previous Workmentioning

confidence: 99%

“…Various sorts of FA planning in place of limiting force are, for example, Hybrid Full Adder (H-FA) and 10 Transistor reduced power Full Adder (10T-FA) and 11 transistor FA (11T-FA) etc. FA works in mode of ultra-low through utilization of subthreshold current then expends low power [2], [3]. Full Adder is manufactured utilizing near to the ground power XOR gate and 2:1 multiplexer.…”

Section: Previous Workmentioning

confidence: 99%

Design of 8-Bit ALU Design using GDI Techniques with Less Power and Delay

2019

IJRTE

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Arithmetic Logic Unit (ALU) is a substantial fragment of microchip. Cutting-edge computerized processors, legitimate and math activity accomplishes making use of ALU. This paper depicts an 8-Bit ALU operating with a lowest power 11-Transistor Full Adder (11-T FA) and Gate dispersion input (GDI) centered MUX. All structures were simulated using Tanner EDA software version-15 with 32 nanometer BSIM4 innovation. Execution examinations were furnished as for voltage, power, postponement and power delay item. In this paper 8-bit ALU operated in subthreshold region, selected 0.7 VDD for maintain the both power as well as delay. In 8-bit ALU of GDI proposed model, less than 82% power consumption reduced as compare with CMOS 8-Bit ALU due to voltage level improvement.

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“…The region just below V t of a transistor is called the sub-threshold region [4]. After the gate to source voltage V gs is less than threshold Voltage V t , then the leakage current This indicates that the parameters µ, K, q are constants and only V t and W are dependent on I leakage .…”

Section: A High V T Cell Conceptmentioning

confidence: 99%

Delay, Power performance of 8-Bit ALU Using Carry Look-Ahead Adder with High Vt Cell

Shankar¹

2018

IJRASET

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AREA optimized low power arithmetic and logic unit

Cited by 27 publications

References 9 publications

Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs

Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs

Design of 8-Bit ALU Design using GDI Techniques with Less Power and Delay

Delay, Power performance of 8-Bit ALU Using Carry Look-Ahead Adder with High Vt Cell

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