Arrayable Voltage-Controlled Ring-Oscillator for Direct Time-of-Flight Image Sensors

Abstract

Direct time-of-flight (d-ToF) estimation with high frame rate requires the incorporation of a time-to-digital converter (TDC) at pixel level. A feasible approach to a compact implementation of the TDC is to use the multiple phases of a voltage-controlled ring-oscillator (VCRO) for the finest bits. The VCRO becomes central in determining the performance parameters of a d-ToF image sensor. In this paper we are covering the modeling, design and measurement of a CMOS pseudo-differential VCRO. The oscillation frequency, the jitter due to mismatches and noise and the power consumption are analytically evaluated. This design has been incorporated into a 64×64-pixel array. It has been fabricated in a 0.18µm standard CMOS technology. Occupation area is 28×29μm 2 and power consumption is 1.17mW at 850MHz. The measured gain of the VCRO is of 477MHz/V with a frequency tuning range of 53%. Moreover it features a linearity of 99.4% over a wide range of control frequencies, namely from 400MHz to 850MHz. The phase noise is of-102dBc/Hz at 2MHz offset frequency from 850MHz. The influence of these parameters in the performance of the TDC has been measured. The minimum time bin of the TDC is 147ps with a RMS DNL/ INL of 0.13/ 1.7LSB.

Quantum-inspired computational imaging

“…Moreover, the single-bit nature of the acquisition permits very high frame acquisition rates (rates up to 100 kHz have been reported) (39). Progress has also been made in the full on-chip integration of TCSPC electronics, thus providing the additional functionality of temporal resolutions as low as 50 ps (21,(40)(41)(42)(43). This implies that, when combined with a high repetition rate laser for the active illumination of the scene, video rates reaching up to 20 billion frames per second can be achieved (44).…”

256 $\times$ TDC Array With Cyclic Interpolators Based on Calibration-Free $2{\times}$ Time Amplifier

“…The interpolator has an effective resolution of 9bits, but a 10bit output word is used in order to allow room for static timing offsets that can occur due to synchronization delays or routing/gate delays. Since the Start and Stop channel interpolators are identical, the nominal static offset due to synchronization logic and gate delays is equal in both interpolators and any possible offset is removed when the final output word is calculated according to (1). A small offset error might remain due to random mismatches and process gradients.…”

“…The resolution of such converter is defined by the propagation delay of a single delay element in the delay line/ring oscillator. In order to make the size of the LSB, and therefore the gain of the converter, well defined and uniform across the whole TDC array, a replica biasing method is often used [1]- [3]. The replica bias block creates a shared bias for the TDCs by using a PLL/DLL to fix the propagation delay of the delay line to be proportional to the reference clock's period.…”

Design and analysis of differential ring voltage controlled oscillator for wide tuning range and low power applications

“…DROs are more popular than SEROs because of their advantages such as possibility of using an odd or even number of cells, better immunity to common mode noise, lower swing, and 50% duty cycle at the output. Moreover, it is easy to achieve very high‐frequency performance with both in‐phase and quadrature outputs in DROs …”

“…Moreover, it is easy to achieve very high-frequency performance with both in-phase and quadrature outputs in DROs. [14][15][16][17][18][19][20][21] From the past, DRO designers have been working to improve the important parameters in designing DROs, such as phase noise, power dissipation, voltage operation, occupied area, oscillation frequency, multiphase clock generation, supply sensitivity, and tuning range. Therefore, different DROs topologies have been proposed to improve these parameters.…”