As-grown-generation (AG) model of NBTI: A shift from fitting test data to prediction

Zhang, Chenglong; Ji, Zhigang; Zhang, Wensheng

doi:10.1016/j.microrel.2017.11.026

Cited by 25 publications

(33 citation statements)

References 44 publications

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“…It has been shown that the ∆Vth grows linearly against logarithmic time within the first ~1 sec [12]. Unfortunately, the charging (b) kinetics starts deviating from this linear relationship [12], as new traps are generated [26], [27].…”

Section: A Methodologymentioning

confidence: 99%

An Assessment of the Statistical Distribution of Random Telegraph Noise Time Constants

et al. 2020

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As transistor sizes are downscaled, a single trapped charge has a larger impact on smaller devices and the Random Telegraph Noise (RTN) becomes increasingly important. To optimize circuit design, one needs assessing the impact of RTN on the circuit and this can only be accomplished if there is an accurate statistical model of RTN. The dynamic Monte Carlo modelling requires the statistical distribution functions of both the amplitude and the capture/emission time (CET) of traps. Early works were focused on the amplitude distribution and the experimental data of CETs were typically too limited to establish their statistical distribution reliably. In particular, the time window used has been often small, e.g. 10 sec or less, so that there are few data on slow traps. It is not known whether the CET distribution extracted from such a limited time window can be used to predict the RTN beyond the test time window. The objectives of this work are three fold: to provide the long term RTN data and use them to test the CET distributions proposed by early works; to propose a methodology for characterizing the CET distribution for a fabrication process efficiently; and, for the first time, to verify the long term prediction capability of a CET distribution beyond the time window used for its extraction.

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Section: A Methodologymentioning

confidence: 99%

An Assessment of the Statistical Distribution of Random Telegraph Noise Time Constants

et al. 2020

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“…2, which is widely observed when measured by the fast (~µs) pulse technique that minimizes recovery [13,14]. Such non-power law behavior is successfully explained by the As-grown-Generation (AG) model [14], where defects are divided into two groups: Asgrown hole traps (AHT) and Generated defects (GD). Their separation is based on their different energy profiles, charging and discharging properties, as detailed in early works [15,16].…”

Section: Principle Of Voltage Step Stress Techniquementioning

confidence: 97%

“…This is challenged by the non-power law behavior of NBTI shown in Fig. 2, which is widely observed when measured by the fast (~µs) pulse technique that minimizes recovery [13,14]. Such non-power law behavior is successfully explained by the As-grown-Generation (AG) model [14], where defects are divided into two groups: Asgrown hole traps (AHT) and Generated defects (GD).…”

Section: Principle Of Voltage Step Stress Techniquementioning

confidence: 99%

“…Charging AHTs can dominate the NBTI initially, leading to the deviation from the power law in Fig. 2 [14,16]. AHTs are pre-existing and not caused by stresses, so that it should not be included in the ageing process [14].…”

Section: Principle Of Voltage Step Stress Techniquementioning

confidence: 99%

“…2 [14,16]. AHTs are pre-existing and not caused by stresses, so that it should not be included in the ageing process [14]. After removing AHTs, the power law is restored for the ageing kinetics.…”

Section: Principle Of Voltage Step Stress Techniquementioning

confidence: 99%

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Voltage step stress: a technique for reducing test time of device ageing

Zhang

Duan

et al. 2019

2019 International Conference on IC Design and Technology (ICICDT)

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Device ageing leads to circuit malfunction and must be controlled. During ageing, defects build up slowly and the test is time consuming and costly. The typical ageing tests are repeated ~5 times under different voltages. To reduce the test time, the voltage step stress (VSS) technique is proposed, which replaces the multiple tests under different voltage by a single test and saves time. This paper reviews the recent development of the VSS technique. After presenting its underlying principle, its applicability will be demonstrated for both the negative bias temperature instability and hot carrier ageing.

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