Controversial issues in negative bias temperature instability

Stathis, J. H.; Mahapatra, S.; Grasser, T.

doi:10.1016/j.microrel.2017.12.035

Cited by 81 publications

(29 citation statements)

References 21 publications

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“…Several degradation mechanisms like hot-carrier injection (HCI) and bias temperature instability (BTI) arise when an electrical stress is applied to nMOSFET's. Charge trapping, defect formation in the gate oxide and at the interface play a role, although there is still some discussion to what degree [1]. There is however consensus that for both mechanisms hydrogen plays a pivotal role in the degradation and recovery of the devices [2].…”

Section: Introductionmentioning

confidence: 99%

Towards understanding recovery of hot-carrier induced degradation

Jong

Salm

Schmitz

2018

Microelectronics Reliability

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A B S T R A C TThis article treats the recovery of hot-carrier degraded nMOSFETs by annealing in a nitrogen ambient. The recovery rate is investigated as a function of the annealing temperature, where the recovery for increasing temperatures is in agreement with the passivation processes. At the original post-metal anneal temperature of T = 400°C, the device's original performance is fully restored. Higher temperatures induce a permanent, unrecoverable change to the devices, manifested in a gradual V T shift. The recovery rate is found to be independent of both the transistor gate length and the cooling rate (quench, slow and stepped cooling) upon annealing. These findings are used to gain further understanding of the mechanisms behind the recovery of hot-carrier damage. The recovery rate exhibits Arrhenius behavior and the recovery data are consistent with Stesmans' recovery model.

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Section: Introductionmentioning

confidence: 99%

Towards understanding recovery of hot-carrier induced degradation

Jong

Salm

Schmitz

2018

Microelectronics Reliability

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“…Although an extrapolation of the recovery trace to t M = 0, or some correction method might be able to achieve the true zero-delay degradation [2], [29], direct measurement is desired and necessary to verify the assumption for the extrapolation or correction. With the commercial instruments by far, the contributions of the defects with time constants smaller than 1 µs are difficult to measure [30]. Therefore, novel techniques with much faster measurement speed are required to obtain the intrinsic behavior of NBTI directly.…”

Section: Methodsmentioning

confidence: 99%

“…As the measurement time is reduced from 10 µs to 10 ns, a huge impact of the measurement time could be observed. Such phenomena indicates the existence of the preexisting traps in the gate dielectric with capture time constants of ns-scale, which have been theoretical predicted but not been confirmed because of the limitation of the experimental window due to measurement speed [28], [30], [31]. The time exponents, n, were extracted and summarized in Fig.…”

Section: A Influence Of the V Th Measurement Speed On Nbti Charactermentioning

confidence: 99%

Ultra-Fast (ns-Scale) Characterization of NBTI Behaviors in Si pFinFETs

Liu

et al. 2020

IEEE J. Electron Devices Soc.

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In this paper, NBTI behaviors of Si pFinFETs are characterized with the measurement time down to ns-scale utilizing the fast V th measurement (FVM) technique. It is found that the NBTI behaviors in terms of V th shift is strongly influenced by the measurement speed even in the nano-second scale (ns-scale). The measurement phase itself during the NBTI characterization could bring in an additional V th shift (V th) or V th recovery. From the ns-scale characterization results in different stress and temperature, it is shown that the rapid recoverable components of NBTI should be attributable to the rapid hole trapping/detrapping, which are related to the defects with time constants of ns-scale. INDEX TERMS pFinFETs, reliability, NBTI, ultra-fast measurement.

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“…These traps cause a number of effects detrimental to the operating characteristics and reliability of the devices [1,2]. The most prominent reliability issues in these devices related to charge trapping are the so called bias temperature instabilities (BTI) [3][4][5] and random telegraph noise (RTN) [6][7][8]. While BTI can be observed in large-area and nanoscale devices, RTN is mainly studied on scaled technologies.…”

Section: Introductionmentioning

confidence: 99%

Semi-Automated Extraction of the Distribution of Single Defects for nMOS Transistors

Stampfer

Schanovsky²,

Waltl

2020

Micromachines

Self Cite

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Miniaturization of metal-oxide-semiconductor field effect transistors (MOSFETs) is typically beneficial for their operating characteristics, such as switching speed and power consumption, but at the same time miniaturization also leads to increased variability among nominally identical devices. Adverse effects due to oxide traps in particular become a serious issue for device performance and reliability. While the average number of defects per device is lower for scaled devices, the impact of the oxide defects is significantly more pronounced than in large area transistors. This combination enables the investigation of charge transitions of single defects. In this study, we perform random telegraph noise (RTN) measurements on about 300 devices to statistically characterize oxide defects in a Si/SiO 2 technology. To extract the noise parameters from the measurements, we make use of the Canny edge detector. From the data, we obtain distributions of the step heights of defects, i.e., their impact on the threshold voltage of the devices. Detailed measurements of a subset of the defects further allow us to extract their vertical position in the oxide and their trap level using both analytical estimations and full numerical simulations. Contrary to published literature data, we observe a bimodal distribution of step heights, while the extracted distribution of trap levels agrees well with recent studies.

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Controversial issues in negative bias temperature instability

Cited by 81 publications

References 21 publications

Towards understanding recovery of hot-carrier induced degradation

Towards understanding recovery of hot-carrier induced degradation

Ultra-Fast (ns-Scale) Characterization of NBTI Behaviors in Si pFinFETs

Semi-Automated Extraction of the Distribution of Single Defects for nMOS Transistors

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