AsAP: An Asynchronous Array of Simple Processors

Yu, Zhou; Meeuwsen, M.J.; Apperson, R.W.; Sattari, O.; Lai, M.; Webb, J.; Work, Eric; Truong, Dean N.; Mohsenin, Tinoosh; Baas, Bevan M.

doi:10.1109/jssc.2007.916616

Cited by 60 publications

(19 citation statements)

References 26 publications

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“…The low complexity 2D mesh has been used by most fabricated many-core systems including RAW [5], AsAP [6], TILE64 [7], AsAP2 [8] and Intel 48-core Single-Chip Cloud Computer (SCC) [9].…”

Section: Related Workmentioning

confidence: 99%

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

Xiao

Baas

2013

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

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Abstract. Network-on-Chips (NoCs) are used to connect large numbers of processors in many-core processor architecture because they perform better than less scalable methods such as global shared buses. Among all NoC design parameters, NoC topologies define how nodes are placed and connected and greatly affect the performance, energy efficiency, and circuit area of many-core processor arrays. Due to its simplicity and the fact that processor tiles are traditionally square or rectangular, 2D mesh is mostly used for existing on-chip networks. However, efficiently mapping applications can be a challenge for cases that require communication between processors that are not adjacent on the 2D mesh. Motivated by the fact that applications often have largely localized communication patterns, we have proposed an 8-neighbor mesh topology and a 6-neighbor topology with hexagonal-shaped processor tiles, both of which increase local connectivity while keep much of the simplicity of a mesh-based topology. We have physically designed a 16-bit DSP processor and the corresponding processor arrays which utilize all three topologies. A 1080p H.264/AVC residual video encoder and a 54 Mbps 802.11a/11g OFDM wireless LAN baseband receiver are mapped onto all topologies. The 6-neighbor hexagonal grid topology incurs a 2.9% area increase per tile compared to the 4-neighbor 2D mesh, but its much more effective interprocessor interconnect yields an average total application area reduction of 21%, an average power reduction of 17%, and a total application interprocessor communication distance reduction of 19%.

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“…The low complexity 2D mesh has been used by most fabricated many-core systems including RAW [5], AsAP [6], TILE64 [7], AsAP2 [8] and Intel 48-core Single-Chip Cloud Computer (SCC) [9].…”

Section: Related Workmentioning

confidence: 99%

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

Xiao

Baas

2013

VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design

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“…Concerning dynamically reconfigurable MPSoC architectures, the MORPHEUS [8] project aims to develop new heterogeneous reconfigurable SoCs with various sizes of reconfiguration granularity. Yu et al [9] propose an asynchronous array of simple processors (AsAP) which maintains the flexibility and programming ease of a programmable processor. There has been a spurt in work focussed on exploiting the powerful capabilities of dynamic reconfiguration for image processing and multimedia applications [10], [11], [12].…”

Section: Related Workmentioning

confidence: 99%

FSM-controlled architectures for linear invasion

Arifin

Membarth

Amouri

et al. 2009

2009 17th IFIP International Conference on Very Large Scale Integration (VLSI-SoC)

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Abstract-Invasive computing is a novel concept in multiprocessor architecture and programming. Invasion will become an important step towards self-organizing behavior which will be needed in the next generation of massively parallel MPSoCs with unrivaled performance and resource efficiency numbers as one of the main challenges for MPSoC apart from their programming. In this paper we introduce and model a finite state machine for controlling the invasive process in different architectural granularities. The applicability of our FSM is tested in case studies for a reconfigurable MPSoC platform and a fine-grained platform. The results show substantial flexibility gains with only marginal additional hardware cost.

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“…In [11], multi-variant AES cipher was executed in batch by avoiding thread divergence on a GPU device of Tesla K20c, where the speed-up can reach 0.44 cycles/byte when using 4 non-default streams. Besides, an AES engine was implemented on a many core processor array called AsAP [12] by exploring data-level and task-level parallelism [13], which presented various implementations for high performance, throughput per unit of chip area and energy efficiency.…”

Section: Introductionmentioning

confidence: 99%

Efficient AES cipher on coarse-grained reconfigurable architecture

Wang

Cao

Yang

2017

IEICE Electron. Express

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By exploring the mapping schemes with dataflow graph (DFG) transformation and different granularity of task-level parallelism, we presented various AES implementations on a coarse grained reconfigurable architecture (CGRA) to meet the requirements raging from high performance to low power. In comparison with published AES cipher implementations on programable processors, our AES cipher has 14.7∼121.4× higher energy efficiency. Moreover, the design shows the advantage over other CGRAs with 1.3∼4.5× energy efficiency improvement.

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AsAP: An Asynchronous Array of Simple Processors

Cited by 60 publications

References 26 publications

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks

FSM-controlled architectures for linear invasion

Efficient AES cipher on coarse-grained reconfigurable architecture

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