Assembly and reliability challenges in 3D integration of 28nm FPGA die on a large high density 65nm passive interposer

Chaware, Raghunandan; Nagarajan, K. V.; Ramalingam, Suresh

doi:10.1109/ectc.2012.6248841

Cited by 106 publications

(31 citation statements)

References 8 publications

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“…This means that a 12 inch silicon wafer with 730cm 2 of area would produce on average 0.3 working 6cm 2 dies, while the same wafer would produce on average 107 working 1.5cm 2 dies. Therefore, as a 6cm 2 chip would be composed of four 1.5cm 2 dies, the wafer would yield 26.75 systems on average, as the "assembly yield" of placing these four die on an interposer is very high [4]. Hence the number of interposer-based FPGAs created from the same silicon wafer would be almost 100× greater than a monolithic FPGA of the same size.…”

Section: Silicon Interposer Backgroundmentioning

confidence: 99%

“…Hence the area occupied by microbumps at one edge of one die is 13440 × (45µm) 2 = 27mm 2 . If we assume each die is 7 × 12mm, as presented by Chaware et al in [4], the bumps have to be spread out near the edge and need to go as far as 2.25mm away from the edge of the die. This greater distance from the border increaes the length of the inter-die connections, and along with the presence of the micro-bumps and their capacitance, leads to an increased delay for these crossing wires vs. that of a typical on-die routing wire.…”

Section: Virtex-7 Interposer-based Fpgasmentioning

confidence: 99%

“…As described in Section 3 we are studying the impact of several key interposer parameters on the performance of the multi-FPGA system, including (i) the percentage of the wiring normally present between rows of the FPGA which are cut when crossing between dice, and (ii) the extra delay (vs. a normal connection between adjacent rows) added when one must traverse the interposer. To locate where Virtex-7 lies in this architecture space, we combined published information on the implementation of Xilinx's interposer-based FPGAs [4] with a detailed analysis of the XC7V2000T FPGA routing resources visible in the Vivado Device View. [13].…”

Section: Virtex-7 Interposer-based Fpgasmentioning

confidence: 99%

“…Chaware et al presented Xilinx's approach to silicon interposer FPGAs [4]. They describe the physical characteristics of their implementation, including the bump pitch and estimates of the amount of die-to-die connectivity and the dieto-die delay.…”

Section: Introductionmentioning

confidence: 99%

“…They describe the physical characteristics of their implementation, including the bump pitch and estimates of the amount of die-to-die connectivity and the dieto-die delay. However [4] does not analyze the architecture question of the routability of the resulting system, nor describe possible CAD optimizations, which are the questions we investigate.…”

Section: Introductionmentioning

confidence: 99%

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Cad and routing architecture for interposer-based multi-FPGA systems

Pereira

Betz

2014

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays

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Interposer-based multi-FPGA systems are composed of multiple FPGA dice connected through a silicon interposer. Such devices allow larger FPGA systems to be built than one monolithic die can accomodate and are now commercially available. An open question, however, is how efficient such systems are compared to a monolithic FPGA, as the number of signals passing between dice is reduced and the signal delay between dice is increased in an interposer system vs. a monolithic FPGA.We create a new version of VPR to investigate the architecture of such systems, and show that by modifying the placement cost function to minimize the number of signals that must cross between dice we can reduce routing demand by 18% and delay by 2%. We also show that the signal count between dice and the signal delay between dice are key architecture parameters for interposer-based FPGA systems. We find that if an interposer supplies (between dice) 60% of the routing capacity that the normal (within-die) FPGA routing channels supply, there is little impact on the routability of circuits. Smaller routing capacities in the interposer do impact routability however: minimum channel width increases by 20% and 50% when an interposer supplies only 40% and 30% of the within-die routing, respectively. The interposer also impacts delay, increasing circuit delay by 34% on average for a 1 ns interposer signal delay and a four-die system. Reducing the interposer delay has a greater benefit in improving circuit speed than does reducing the number of dice in the system.

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Section: Silicon Interposer Backgroundmentioning

confidence: 99%

Section: Virtex-7 Interposer-based Fpgasmentioning

confidence: 99%

Section: Virtex-7 Interposer-based Fpgasmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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