Assembly and reliability of flip chip on boards using ACAs or eutectic solder with underfill

Zhong, Zhang

doi:10.1108/13565369910293297

Cited by 35 publications

(19 citation statements)

References 4 publications

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“…In these products, electronic packaging plays important roles such as supplying power to integrated circuit (IC) chips and distributing signals among microelectronic devices. As IC fabrication advances rapidly, electronic packaging faces more and more challenges [1][2][3][4].…”

Section: Introductionmentioning

confidence: 99%

Effects of Sintering Process Conditions on Size Shrinkages of Low-Temperature Co-Fired Ceramic Substrate

Zhong

Arulvanan

Ang

2006

Materials and Manufacturing Processes

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The effects of sintering process conditions on the size shrinkages of low-temperature co-fired ceramic (LTCC) substrate were investigated. The process variables investigated were thickness of the stacked raw tapes, lamination pressure, lamination-pressure holding time, pre-heating time, debinding time, sintering dwell time, and sintering temperature ramp. Results revealed that the size shrinkage percentage of the LTCC samples in the lateral directions was always smaller than that in the thickness direction. The lateral shrinkage deviations were less than 2.1% for all the experiments conducted in this study. Pre-heating time, lamination-pressure holding time, debinding time, sintering dwell time and sintering temperature ramp had almost no effects on the lateral size shrinkage of the LTCC samples, and the average of the lateral shrinkage values was 15.3%, with a standard deviation of 0.17%. Lamination pressure and stacked raw-tape thickness had effects on the lateral size shrinkage of the LTCC samples, and empirical equations for calculation of the size shrinkage values were obtained by curve fitting.

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Section: Introductionmentioning

confidence: 99%

Effects of Sintering Process Conditions on Size Shrinkages of Low-Temperature Co-Fired Ceramic Substrate

Zhong

Arulvanan

Ang

2006

Materials and Manufacturing Processes

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“…There are plenty of writings discussing the effect of underfill, which helps to mitigate the effects of large stresses induced by the mismatch of thermal expansion coefficient between organic / inorganic substrates and chips [1][2][3][4]. Moreover, underfill provides peripheral protection to the solder joints, delivering a practical solution to extend the application of flip-chip technology [5].…”

Section: Introductionmentioning

confidence: 99%

Achievement of low temperature chip stacking by a wafer-applied underfill material

Cheng

Kao

Chang

et al. 2011

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

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This paper will highlight recent developments of an efficient assembly technology for chip stacking which utilizes a novel wafer applied underfill (WAUF). The a-stage WAUF was spin coated on an 8" wafer with a bump structure of 5 um Cu / 3 um Ni / 5 um Sn2.5Ag Pb-free solder, and then baked at 125ºC for 40 minutes to form a 30 um thick b-stage film. After wafer dicing, four chips with WAUF were assembled via a SÜSS FC-150 bonder on a Si interposer. With the aid of the flux agent in the WAUF, the peak bonding temperature was lowered to 240ºC, which was beneficial for the reduction of residual thermal stress as compared to that imposed by direct bonding at 280ºC. Previous work showed that no delamination of WAUF was found in the chip stacking architecture after the precondition test. In the most recent study, a temperature cycling test (TCT, JESD22-A104-B, Condition B, Soak mode 2) was used to assess the reliability of the 20 um pitch microjoints sealed by the WAUF. After 250 TCT cycles, 87.5% test vehicles failed with a failure mode of the microjoints shown to be interfacial fracture. This was a similar result to the failure mode of microjoints sealed by capillary underfill, though the WAUF failed much earlier.The root-cause of the failure can be attributed to the inferior bonding accuracy, as the majority of the Sn2.5Ag solder alloy at the contact area completely reacted with Ni to form Ni 3 Sn 4 at this stage but did not link up with each other (a proposed failure mechanism will be given in another ITRI's paper). However, the lifespan of the microjoints could be prolonged if the remaining Sn2.5Ag Pb-free solder alloy is sufficient to sustain the bump structure after bonding, even though the WAUF was not post-cured. The authors believe that the newly developed underfill material and the corresponding assembly technology will reveal a proper technique for stacking homogeneous ICs (such as DRAM) efficiently and reliably.

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“…These passive-cooling technologies used liquid as coolant to provide cooling effects. As microelectronic devices continue to shrink and their power assumption continues to increase [7][8][9][10], actively cooling them becomes more challenging. Some of the traditional methods can no longer be used.…”

Section: Introductionmentioning

confidence: 99%

Investigation of the performance of micro-thermoelectric coolers

Zhong

Wang

Low

2008

Micro- And Nanotechnology: Materials, Processes, Packaging, and Systems IV

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Assembly and reliability of flip chip on boards using ACAs or eutectic solder with underfill

Cited by 35 publications

References 4 publications

Effects of Sintering Process Conditions on Size Shrinkages of Low-Temperature Co-Fired Ceramic Substrate

Effects of Sintering Process Conditions on Size Shrinkages of Low-Temperature Co-Fired Ceramic Substrate

Achievement of low temperature chip stacking by a wafer-applied underfill material

Investigation of the performance of micro-thermoelectric coolers

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