Asymmetric gate capacitance and dynamic characteristic fluctuations in 16 nm bulk MOSFETs due to random distribution of discrete dopants

Abstract

Characteristic variability of a transistor is a crucial issue for nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs). In this study, we explore the asymmetric sketch of the random dopant distribution near the source end and the drain end in 16 nm MOSFETs. Discrete dopants near the source and drain ends of the channel region induce rather different fluctuations in gate capacitance and dynamic characteristics. Based upon the observed asymmetry properties, a lateral asymmetry channel doping profile engineering is then proposed to suppress the random-dopant-induced characteristic fluctuations in the examined devices and circuits. The results of this study indicate that the fluctuations in average gate capacitance, circuit gain, 3 db bandwidth and unity-gain bandwidth for the cases with dopants near the drain side could be simultaneously reduced by 62.6%, 22.2%, 63.1% and 41.4%, respectively. Consequently, such a lateral asymmetry channel doping profile could be considered to design intrinsic parameter fluctuation resistant transistors.

Dual-Material Gate Approach to Suppression of Random-Dopant-Induced Characteristic Fluctuation in 16 nm Metal–Oxide–Semiconductor Field-Effect-Transistor Devices

“…The results of this study show that devices with a DMG structure possess interesting fluctuation suppression. Note that lateral asymmetric channel (LAC) and inverse LAC (inLAC) devices have also been reported in our recent work 39) for suppressing RD-induced characteristic fluctuation. Therefore, except for the proposed DMG approach in this work, by simultaneously integrating the channel-dopingprofile engineering technique 39) in the device's channel doping profile, techniques for fabricating DMG devices with an LAC and inLAC, which exhibit good effectiveness of fluctuation suppression, are further explored.…”

“…A device with a high WK near the source or drain side may induce relatively high intrinsic electrostatic potential barriers for both the on-and off-states, as shown in Figs. 2(a I shows a summary of the results obtained using different suppression techniques for devices with the DMG structure; compared with those obtained in our recent studies, 18,[39][40][41] the achieved improve-ments of the DMG structure for suppressing RD-induced V th , I on , and I off fluctuations are 28, 12.3, and 59%, respectively. Devices showing the LAC and inLAC doping profiles have been reported in our recent work 39) on the suppression of RD-induced characteristic fluctuations, where the DC and AC characteristics were examined and compared for 16 nm MOSFET devices and circuits.…”

“…Devices showing the LAC and inLAC doping profiles have been reported in our recent work 39) on the suppression of RD-induced characteristic fluctuations, where the DC and AC characteristics were examined and compared for 16 nm MOSFET devices and circuits. We observed in that work that a device with dopants near the drain end exhibits less characteristic fluctuations owing to the well-controlled major fluctuation source of the gate-drain capacitance.…”

“…We observed in that work that a device with dopants near the drain end exhibits less characteristic fluctuations owing to the well-controlled major fluctuation source of the gate-drain capacitance. 39) Therefore, to further suppress the fluctuation, the channelengineering techniques of the LAC and inLAC together with the DMG approach are advanced for the 16 nm devices studied. The adopted near-source-end doping profile implemented with the DMG (i.e., DMG + LAC) device and the near-drain-end channel doping profile implemented with the DMG (i.e., DMG + inLAC) device are shown in Figs.…”

Nanosized-Metal-Grain-Induced Characteristic Fluctuation in 16 nm Complementary Metal–Oxide–Semiconductor Devices and Digital Circuits

“…The feature dimensions of field-effect transistors (FETs) have been rapidly scaled down and thus characteristic variability has become one of the major challenges in complementary metal-oxide-semiconductor (CMOS) technologies. [1][2][3][4][5][6][7] Diverse approaches to examining intrinsic parameter fluctuations in CMOS devices and circuits have recently been presented. [8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23] Devices with a high-/metal gate compose a technology for suppressing such intrinsic parameter fluctuations.…”