Nanosized-Metal-Grain-Induced Characteristic Fluctuation in 16 nm Complementary Metal–Oxide–Semiconductor Devices and Digital Circuits

Abstract

In this work, we investigate the effect of random work functions (WKs) resulting from the nanosized grains of a metal gate on 16 nm metal–oxide–semiconductor field-effect transistor (MOSFET) devices and circuits. The random number and position of nanosized metal grains induce rather different random WKs on a MOSFET gate, which cannot be modeled using an averaged WK; thus, we consider each WK of the metal gate, according to the size of partitioned grains, in three-dimensional device simulation. The results of this study indicate that the random-WK-induced threshold voltage fluctuation of N- and P-MOSFETs are about 1.5 and 1.6 times higher than the results calculated by the recently reported averaged WK fluctuation method. This is because even if the devices have similar threshold voltages, they may exhibit quite different combinations of WKs owing to the random position of nanosized metal grains on the devices' gate. Coupled device-circuit simulation is further adopted to explore the timing fluctuations of complementary metal–oxide–semiconductor (CMOS) inverter circuits. The random position of nanosized metal grains results in 10 and 12% variations in the timing fluctuation and power consumption of the CMOS inverter circuit.

Random Interface-Traps-Induced Electrical Characteristic Fluctuation in 16-nm-Gate High-κ/Metal Gate Complementary Metal–Oxide–Semiconductor Device and Inverter Circuit

“…We first calibrate the nominal DC characteristic of the studied HKMG devices according to ITRS roadmap for low operating power, which was experimentally quantified in our recent study. 32) Note that all adopted material properties, device settings, and characteristics follow our recent study, 8) where the threshold voltage of the 16-nm-gate N-MOSFETs is equal to 250 mV (À250 mV for P-MOSFETs). For ITF simulation, we first randomly generate 753 ITs in a large 2D plane, where the size of plane is (224 nm) 2 , as shown in Fig.…”

“…High-/metal gate (HKMG) technology for maintaining device characteristics and suppressing device's intrinsic parameter fluctuation is introduced. [8][9][10][11][12][13][14][15][16][17][18][19] However, emerging fluctuation source, the random interface traps (ITs) at high-/silicon interface degrades device characteristic. [20][21][22][23][24][25][26][27][28][29][30][31] Recently, one-dimensional (1D) and 2D random ITs at high-/silicon interface were proposed for DC characteristic fluctuation simulation of sub-45-nm CMOS devices.…”